Sr Staff Digital Engineer

Renesas Electronics Corp.; Duluth (GA); On-site; USD 140,000 - 190,000; Full time

Job summary

Renesas Electronics Corp. is seeking a senior RTL design engineer to propose, architect, and design Verilog RTL for a mixed-signal IC. You will contribute to a highly experienced team and help drive clocking controls, FSM design, low power techniques, and high-speed design concepts.

The role requires 12+ years in ASIC/IC design, fluent Verilog RTL coding, and strong experience in synthesis, STA, LEC, and DFT insertion. You will mentor junior engineers and collaborate in design reviews.

Qualifications

• Education: Bachelor or Master in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 12+ years of experience in ASIC/IC design and full IC design flow.
• Fluent in Verilog RTL coding and ASIC design methodology.
• Experience with static timing analysis and place-and-route constraints.
• Experience with gate-level simulations and timing violations.
• Experience with DFT or physical design is a plus.

Responsibilities

• Propose, architect, and design RTL in Verilog for a mixed-signal IC.
• Oversee digital backend design including synthesis, STA, and LEC.
• Participate in design, architecture, and verification reviews.
• Create documentation for design, verification, and test teams.
• Mentor and train junior engineers.

Skills

Verilog RTL

ASIC design

Digital design

Synthesis

STA

Education

Bachelor or Master in Electrical/CS/Engineering

Tools

DFT insertion

Formal verification

Linting

CDC/RDC checking

Job description

Propose, architect, and design RTL in Verilog for use in a mixed-signal integrated circuit

Contribute as part of a highly experienced team of engineers with extensive cross‑functional skill set

Apply clocking controls, FSM design, low power techniques, and high‑speed design concepts

• Participate in design, architecture, and verification reviews
• Oversee digital backend design, including synthesis, static timing analysis, and logic equivalence checking
• Create documentation targeting design, verification, and test teams
• Assist with the proposal, definition, documentation, and implementation of new features
• Mentor and train junior engineers and New College Grad engineers

Job Description

• Propose, architect, and design RTL in Verilog for use in a mixed-signal integrated circuit
• Contribute as part of a highly experienced team of engineers with extensive cross‑functional skill set
• Apply clocking controls, FSM design, low power techniques, and high‑speed design concepts
• Participate in design, architecture, and verification reviews
• Oversee digital backend design, including synthesis, static timing analysis, and logic equivalence checking
• Create documentation targeting design, verification, and test teams
• Assist with the proposal, definition, documentation, and implementation of new features
• Mentor and train junior engineers and New College Grad engineers

Qualifications

• Education: Bachelor or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with minimum 12+ years of experience
• 8+ years of direct experience in ASIC/IC design with deep knowledge of the entire IC design flow
• Experience in architecting digital designs and writing device-level or sub‑system specifications.
• Fluent in Verilog RTL coding and ASIC design methodology
• Expertise in digital design implementation, including logical synthesis and DFT insertion with high coverage
• Experience with static timing analysis and creation of place and route constraints
• Proficiency in formal verification, linting, and CDC/RDC checking
• Knowledge of asynchronous clock crossings and synthesis implications of RTL
• Experience implementing and verifying ECOs on RTL, synthesized, and post‑route netlists
• Competence in developing design constraints for synthesis, STA, and P&R hand‑off
• Experience with gate‑level simulations and understanding the causes and implications of timing violations
• Familiarity with ATPG generation and ATE support (a plus)
• Experience in DFT or physical design (a plus)

Additional Information

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Renesas Electronics deals with dual‑use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.