Lead Digital ASIC Architect for Scientific Instrumentation

Brookhaven Science Associates, LLC; Upton (NY); On-site; USD 115,000 - 145,000; Full time

Job summary

Brookhaven National Laboratory seeks a Senior Digital ASIC Design Engineer to lead architecture, RTL design, and integration of digital ASICs for detector readout and related instrumentation.

You will collaborate with a multidisciplinary team, develop synthesizable RTL in SystemVerilog/Verilog, and work with Cadence and Synopsys environments to ensure successful tapeout and integration at Brookhaven Lab in Upton, NY.

Qualifications

• BS/EE/CE or closely related field with strong digital design background.
• 7+ years in digital ASIC design and RTL development.
• Experience with SystemVerilog/Verilog, EDA tool flows, and timing analysis.

Responsibilities

• Lead architecture, microarchitecture, RTL design and integration of digital ASICs for detector readout and timing.
• Develop and maintain synthesizable RTL, IP, and register maps for complex ASICs/SOC.
• Collaborate with ASIC, firmware, FPGA, and lab teams to tapeout and bring up hardware.
• Support verification plans, DV/testbenches, and timing/physical implementation in CAD/EDA flows.

Skills

SystemVerilog/Verilog

Digital ASIC design

RTL design

Synthesis

Clock-domain crossing

EDA tool flows

Education

Bachelor's degree in electrical/computer engineering or related field

Tools

Cadence

Synopsys

Job description

Brookhaven National Laboratory seeks a Senior Digital ASIC Design Engineer to lead architecture, RTL design, and integration of digital ASICs for detector readout and related instrumentation.

You will collaborate with a multidisciplinary team, develop synthesizable RTL in SystemVerilog/Verilog, and work with Cadence and Synopsys environments to ensure successful tapeout and integration at Brookhaven Lab in Upton, NY.