Senior Digital ASIC Architect for Scientific Readout

Brookhaven National Laboratory; Ridge (NY); On-site; USD 115,000 - 145,000; Full time

Job summary

Brookhaven National Laboratory seeks a Senior Digital ASIC Design Engineer to lead architecture and RTL design for advanced readout ASICs and SoCs in scientific instrumentation. The role emphasizes low-power, radiation-tolerant, and timing-critical digital systems for detector readout and data acquisition.

You will collaborate with analog/mixed-signal, verification, and firmware teams to deliver robust digital blocks, IPs, and interfaces, supporting EIC projects and other programs across the lab.

Qualifications

• Bachelor's degree in electrical engineering, computer engineering, applied physics, or a closely related field of study.
• Minimum seven (7) years of progressively responsible related work experience in digital ASIC design.
• Demonstrated experience developing synthesizable RTL in SystemVerilog/Verilog for complex ASICs or SOCs.
• Familiarity with CAD/EDA tools and design flows across RTL to physical implementation.
• Experience with low-power, radiation-aware design and timing-critical systems.
• Excellent communication and teamwork in a multidisciplinary environment.

Responsibilities

• Lead architecture, RTL design, and integration of digital ASICs for detector readout and related programs.
• Develop design specifications with scientists and stakeholders for detector, timing, power, and system integration.
• Design synthesizable RTL in SystemVerilog/Verilog for data formatting, buffering, and high-speed interfaces.
• Develop reusable digital IP, register maps, bus interfaces, and clock/reset architectures.
• Perform synthesis, STA, CDC/RDC analysis, power estimation, linting, and timing-driven physical implementation.
• Collaborate with physical design, analog/mixed-signal teams for floorplanning and timing closure.
• Coordinate verification plans, test benches, coverage reviews, and debugging before tapeout.
• Support FPGA prototyping, lab evaluation, and integration with sensors and data acquisition systems.
• Lead technical documentation, reviews, and contribute to new proposals using emerging microelectronics tech.

Skills

Digital ASIC design

RTL design

SystemVerilog/Verilog

Clocking & reset strategies

Low-power design

Radiation-tolerant design

Debugging large digital systems

Team collaboration

Education

Bachelor's in electrical engineering or related field

Master's or Ph.D. preferred

Tools

Cadence

Synopsys

Siemens

FPGA prototyping

Tcl scripting

Python scripting

Job description

Brookhaven National Laboratory seeks a Senior Digital ASIC Design Engineer to lead architecture and RTL design for advanced readout ASICs and SoCs in scientific instrumentation. The role emphasizes low-power, radiation-tolerant, and timing-critical digital systems for detector readout and data acquisition.

You will collaborate with analog/mixed-signal, verification, and firmware teams to deliver robust digital blocks, IPs, and interfaces, supporting EIC projects and other programs across the lab.