Lead DFT Engineer — Space-Grade ASICs

SpaceX; Irvine (CA); On-site; USD 210,000 - 340,000; Full time

Benefits offered by this job

Stock options

Employee Stock Purchase Plan

Medical, Vision, Dental coverage

401(k) retirement plan

Paid parental leave

Paid vacation and holidays

Job summary

SpaceX is seeking a Principal DFT Engineer (Silicon Engineering) to lead the implementation and optimization of DFT architectures for next‑gen ASICs used in Starlink and space infrastructures.

Responsibilities include ATPG, scan design, and RTL/physical design validation, with heavy emphasis on Verilog/SystemVerilog and UPF/formal verification, plus collaboration with cross‑functional teams.

Qualifications

• Bachelor's degree in electrical engineering, computer engineering or computer science.
• 10+ years of experience working with ASICs.
• 10+ years of experience in scan insertion and DFT setup, integration and validation.

Responsibilities

• Lead implementation and optimization of DFT architectures using scan insertion, compression/decompression logic, memory BIST, and logic BIST with Siemens Tessent.
• Own ATPG tools and methodologies, including pattern generation for stuck-at, transition, and path delay fault models; provide post‑silicon testing support.
• Evaluate design readiness for scan insertion through RTL and physical design Scan DRC checks.
• Integrate and verify DFT fabrics and IP within Subsystems.
• Run and debug non‑timing and SDF annotated gate‑level simulations.
• Develop test scripts and automate processes using Perl, Python, Tcl, or C++.

Skills

ASICs experience

DFT/ATPG

RTL debugging

Verilog/SystemVerilog

UPF/DFR knowledge

DRC/Formal verification

ATE testers experience

Clock/power optimization

Scripting (Perl/Python/Tcl/C++)

Education

Bachelor's degree in electrical engineering, computer engineering or computer science

Tools

Siemens Tessent

Job description

SpaceX is seeking a Principal DFT Engineer (Silicon Engineering) to lead the implementation and optimization of DFT architectures for next‑gen ASICs used in Starlink and space infrastructures.

Responsibilities include ATPG, scan design, and RTL/physical design validation, with heavy emphasis on Verilog/SystemVerilog and UPF/formal verification, plus collaboration with cross‑functional teams.