Lead DFT Engineer - SoC Test & Silicon Debug

Broadcom; San Jose (CA); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

Annual bonus and equity grants

Competitive benefits package

401(k) and ESPP

Job summary

Broadcom's San Jose Development Center is seeking a Principal DFT Engineer to lead DFT programs from chip-level specification through implementation and verification to production release.

The role requires deep experience in IO/Analog DFT, ATPG, Scan, BIST, test vector generation, and close collaboration with Physical Design, STA, and manufacturing. Proficiency in TCL/Perl/Python/C++ is expected.

Qualifications

• Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)
• Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.)
• Well-versed in ATPG vector generation, simulation, and debugging. (TetraMax, Fastscan)
• Experience in Verilog coding, testbench generation & simulation
• Memory BIST insertion and verification experience on embedded (SRAM, CAM, eDRAM, ROM)
• Boundary scan Verification and test vector generation. Should have good knowledge in IEEE1149.1 and IEEE1149.6
• Basic knowledge Test-STA and constraints
• Strong background on IEE1687, IJTAG, ICL and PDL
• The ability to work in a multi-disciplined, cross-department environment
• Solid knowledge in analog and digital circuit design, and device physics fundamentals
• Good understanding of Si processing, logical and physical synthesis, and transistor reliability principles
• Excellent problem solving, debug, root cause analysis and communication skills
• Experience working on the ATE is a plus
• Experience with Serdes, DDR, PCIE, ENET, CXL IOBIST verification and silicon debug is a plus
• Experience working on Tessent SSN is highly desired

Responsibilities

• Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC
• Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
• Working closely with STA and DI Engineers design closure for test
• Generating, Verifying & Debugging Test vectors before tape release.
• Validating & Debugging Test vectors on ATE during the silicon bring up phase
• Assisting with silicon failure analysis, diagnostics & yield improvement efforts
• Interfacing with the customer, physical design and test engineering/manufacturing teams located globally
• Working closely with I/P DFT engineers & other stakeholders
• Debugging customer returned parts on the ATE
• Innovating newer DFT solutions to solve testability problems in 7nm & beyond
• Automating DFT & Test Vector Generation flows

Skills

Strong DFT background

Scan Insertion

ATPG vector generation

Verilog coding

Memory BIST

Boundary scan

Test-STA

IEEE1687/IJTAG/PDL

Multi-disciplinary teamwork

Analog/digital design knowledge

Silicon processing/synthesis

Problem solving/debugging

ATE experience

Serdes/DDR/PCIe/ENET/CXL IO BIST

Tessent SSN

Education

Bachelors in Electrical/Electronic/Computer Engineering and 12+ years of relevant industry experience or Masters Degree in Electrical/Electronic/Computer Engineering and 10+ years of relevant industry experience

Job description

Broadcom's San Jose Development Center is seeking a Principal DFT Engineer to lead DFT programs from chip-level specification through implementation and verification to production release.

The role requires deep experience in IO/Analog DFT, ATPG, Scan, BIST, test vector generation, and close collaboration with Physical Design, STA, and manufacturing. Proficiency in TCL/Perl/Python/C++ is expected.