Senior DFT Engineer: AI-Driven ASICs for LEO SatCom

Amazon Kuiper Manufacturing Enterprises LLC; Vista (CA); On-site; USD 185,000 - 250,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Parental leave

Job summary

Amazon Kuiper Manufacturing Enterprises LLC is seeking an experienced DFT engineer to define and implement digital chip SOC DFT solutions for high‑speed satellite communications. You will collaborate with customer and wireless system teams to shape modems, interfaces, processors and DSPs in leading CMOS nodes.

The role requires deep sub‑micron DFT expertise, scripting for DFT insertion/validation, and close work with ASIC, RFIC, and test teams to ensure fault coverage, timing and power targets

Qualifications

• Bachelor's degree in Electrical/Communications Engineering, or related electrical field.
• 5+ years of experience in advanced DFT techniques for deep sub-micron nodes.
• Experience implementing DFT methodology and developing automated scripts for insertion and validation.

Responsibilities

• Architect and define DFT solutions adapted to the use of various LEO chips.
• Contribute to IPs and DFT methodology improvements with AI flow.
• Collaborate with ASIC design teams across sites to integrate DFT logic (MBIST, clock controls, JTAG).
• Work with RFIC teams to ensure maximum fault coverage on custom RF blocks.
• Ensure blocks meet DFT, timing, and power targets with the implementation team.
• Translate ATE patterns to tester format with Test engineering.
• Collaborate with test teams to bring up digital portions of LEO chips.

Skills

DFT techniques

Automation scripts

Wireless/ASIC knowledge

Education

Bachelor's degree in Electrical/Communications Engineering

Master's or Ph.D in Electrical/Communications Engineering

Tools

MBIST

JTAG controllers

AI/ML automation

Job description

Amazon Kuiper Manufacturing Enterprises LLC is seeking an experienced DFT engineer to define and implement digital chip SOC DFT solutions for high‑speed satellite communications. You will collaborate with customer and wireless system teams to shape modems, interfaces, processors and DSPs in leading CMOS nodes.

The role requires deep sub‑micron DFT expertise, scripting for DFT insertion/validation, and close work with ASIC, RFIC, and test teams to ensure fault coverage, timing and power targets