Senior DFT Engineer, AI-Driven ASICs for LEO Wireless

Amazon Kuiper Manufacturing Enterprises LLC; California; On-site; USD 185,000 - 250,000; Full time

Job summary

Amazon Kuiper Manufacturing Enterprises LLC in San Diego, CA, is seeking a DFT-focused ASIC engineer to define and implement digital SOCs for LEO communications. You will design DFT solutions, work with RFIC and ASIC teams, and help push AI-assisted DFT flows.

The role involves collaboration across sites to meet DFT, timing, and power targets, translate ATE patterns for testers, and bring up digital portions of LEO chips. A BS with 5+ years in DFT is required; U.S. export controls apply.

Qualifications

• BS in Electrical/Communications Engineering or related field.
• 5+ years in advanced DFT for deep sub-micron nodes.
• Experience implementing DFT methodology and automated scripts for DFT Insertion and Validation.

Responsibilities

• Architect and define DFT solutions adapted to the specific use of various LEO’s chips.
• Contribute to the improvement and customization of IPs and DFT methodology while embracing AI flow.
• Work with the ASIC design teams in all the sites to incorporate DFT logic like MBIST, clock controls and JTAG controllers.
• Work with RFIC teams to ensure maximum fault coverage on the custom RF blocks.
• Ensure that blocks meet DFT, timing and power targets by working closely with the implementation team.
• Work closely with the Test engineering team to help translate the ATE patterns to tester format.
• Work with the test team to do jointly bring up the digital portions of the LEO chips.

Skills

DFT techniques

Automation scripting

RF/ASIC collaboration

Education

Bachelor's degree in Electrical/Communications Engineering

Master's or Ph.D in Electrical / Communications Engineering

Tools

MBIST

JTAG

Job description

Amazon Kuiper Manufacturing Enterprises LLC in San Diego, CA, is seeking a DFT-focused ASIC engineer to define and implement digital SOCs for LEO communications. You will design DFT solutions, work with RFIC and ASIC teams, and help push AI-assisted DFT flows.

The role involves collaboration across sites to meet DFT, timing, and power targets, translate ATE patterns for testers, and bring up digital portions of LEO chips. A BS with 5+ years in DFT is required; U.S. export controls apply.