DFT/DFx Architect & RTL Lead for High-Speed IP

Advanced Micro Devices, Inc.; Santa Clara (CA); Vor Ort; USD 180.000 - 240.000; Vollzeit

Zusammenfassung

AMD's Circuit Technology team seeks an experienced DFT/DFx Lead to drive methodology and RTL execution for high-speed SerDes and memory IPs. You will own architecture definition, RTL implementation, and test strategies across design, verification, CAD, and test engineering, delivering robust, production-ready IP.

This role combines hands-on Verilog/SystemVerilog RTL coding with MBIST planning, ATPG support, and cross-functional collaboration to enable silicon bring-up and yield-learning

Qualifikationen

• Industry experience in DFT/DFx, RTL design, and SoC test methodology.
• Knowledge of DFT architecture: scan, compression, test clocks, test resets, lock-up latches and test access mechanisms.
• Hands-on with Tessent or comparable DFT tools and methodologies.

Aufgaben

• Define and lead PHY-specific DFT/DFx architecture and methodology for high-speed SerDes, Memory PHY, and die-to-die IPs.
• Implement DFT/DFx features in RTL using Verilog/SystemVerilog.
• Develop and support DFT micro-architecture, scan architecture, test modes, and observability features.
• Support JTAG/IJTAG, ICL/PDL, scan compression, at-speed scan, and hierarchical DFT implementation.
• Plan, implement, and verify MBIST-related features for embedded memories.
• Collaborate with Test Engineering and Product Engineering on silicon bring-up and yield-learning activities.

Kenntnisse

DFT architecture

RTL Verilog/SystemVerilog

ATPG/DFT tools

Siemens Tessent

MBIST

JTAG/IJTAG

Ausbildung

BS/MS/PhD in Electrical Engineering

Tools

Verdi

Synopsys VCS

Jobbeschreibung

AMD's Circuit Technology team seeks an experienced DFT/DFx Lead to drive methodology and RTL execution for high-speed SerDes and memory IPs. You will own architecture definition, RTL implementation, and test strategies across design, verification, CAD, and test engineering, delivering robust, production-ready IP.

This role combines hands-on Verilog/SystemVerilog RTL coding with MBIST planning, ATPG support, and cross-functional collaboration to enable silicon bring-up and yield-learning