Senior DFT Engineer — AI-Driven ASIC for LEO SatCom

Amazon Kuiper Manufacturing Enterprises LLC; Lakeside (FL); On-site; USD 185,000 - 250,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Parental leave

Job summary

Amazon Kuiper Manufacturing Enterprises LLC seeks an experienced DFT engineer to define and implement DFT for our LEO chip SOCs, enabling high-reliability communications for satellite gateways. You’ll work with ASIC, RFIC, and test teams to deliver MBIST and JTAG-enabled fault coverage across latest CMOS generations.

You will develop automated DFT insertion and validation scripts, embrace AI-driven flow, and ensure timing and power targets are met by close collaboration with the implementation

Qualifications

• Bachelor's degree in Electrical/Communications Engineering or related field.
• 5+ years of experience in advanced DFT techniques for deep sub-micron nodes.
• Experience implementing DFT and developing automated scripts for DFT insertion and validation.

Responsibilities

• Architect and define DFT solutions adapted to the specific use of various LEO's chips.
• Contribute to the improvement and customization of IPs and DFT methodology while embracing AI flow.
• Work with the ASIC design teams in all the sites to incorporate DFT logic like MBIST, clock controls and JTAG controllers.
• Work with RFIC teams to ensure maximum fault coverage on the custom RF blocks.
• Ensure that blocks meet DFT, timing and power targets by working closely with the implementation team.
• Work closely with the Test engineering team to help translate the ATE patterns to tester format.
• Work with the test team to do jointly bring up the digital portions of the LEO chips.

Skills

DFT techniques

Automated DFT scripts

Deep sub-micron nodes

Education

Bachelor's degree in Electrical/Communications Engineering

Master's or Ph.D. in Electrical/Communications Engineering

Tools

MBIST

Logic BIST

DFT automation tools

Job description

Amazon Kuiper Manufacturing Enterprises LLC seeks an experienced DFT engineer to define and implement DFT for our LEO chip SOCs, enabling high-reliability communications for satellite gateways. You’ll work with ASIC, RFIC, and test teams to deliver MBIST and JTAG-enabled fault coverage across latest CMOS generations.

You will develop automated DFT insertion and validation scripts, embrace AI-driven flow, and ensure timing and power targets are met by close collaboration with the implementation