Senior I/O Architect for Chiplet ASICs

Eliyan; United States; On-site; USD 180,000 - 280,000; Full time

Benefits offered by this job

Excellent benefits

Job summary

Eliyan is seeking an experienced NuLink PHY IO Architect to define subsystems, drive RTL-to-GDSII ASIC development, and lead cross-functional teams in a fast-paced startup environment. You will shape architecture, oversee design and validation, and push for best-in-class performance, power, and manufacturability.

You will mentor engineers, develop advanced design flows, and ensure protocol interoperability across PCIe, UCIe, DDR, and AMBA domains while collaborating with customers and marketing

Qualifications

• 15+ years of experience in ASIC architecture and leadership
• Strong knowledge of two or more connectivity protocols such as PCIe, UCIe, DDR, AMBA
• Expertise in architecture definition, chip micro-architecture and protocol implementation
• Adept at clocking, floorplanning guidelines, and power-aware design
• Proven track record leading teams through tapeouts and delivering manufacturable IP

Responsibilities

• Define NuLink PHY subsystems and hierarchical protocol bridges (PCIe, AXI4, CHI, CXL, DDR)
• Oversee architecture, design, and validation across RTL to GDSII
• Develop and improve design flows and methodologies for on-time delivery
• Create architecture specs with clear integration guidelines for cross-functional teams
• Mentor engineers on protocol implementation, timing, and physical constraints
• Collaborate with ASIC, firmware, and post-silicon teams to support customer integrations
• Ensure compliance with UCIe, PCIe, CXL, AMBA AXI/APB, and DDR standards

Skills

ASIC Architecture

RTL Design

Protocol Design

Scripting & Automation

Clocking & Floorplanning

Education

B.S. or M.S. in Electrical/Computer Engineering

Tools

RTL-to-GDSII flows

Job description

Eliyan is seeking an experienced NuLink PHY IO Architect to define subsystems, drive RTL-to-GDSII ASIC development, and lead cross-functional teams in a fast-paced startup environment. You will shape architecture, oversee design and validation, and push for best-in-class performance, power, and manufacturability.

You will mentor engineers, develop advanced design flows, and ensure protocol interoperability across PCIe, UCIe, DDR, and AMBA domains while collaborating with customers and marketing