Lead Design Verification Engineer

Oho Group; Austin (TX); Hybrid; USD 140,000 - 220,000; Full time

Job summary

Oho Group is seeking a Lead Verification Engineer to build the verification architecture from the ground up. You will collaborate with design, architecture and physical teams to set technical direction for verifying complex ASICs and grow the verification team.

You will develop scalable UVM-based verification environments, create constrained-random test cases, and build scoreboards and coverage infrastructure to drive first-pass silicon success. Hybrid or remote options are available.

Qualifications

• 10+ years of ASIC verification experience.
• Bachelor's or Master's in Electrical Engineering or Computer Engineering or related field.
• Strong knowledge of AMBA on-chip interconnect protocols.
• Proficient in SystemVerilog, SystemC and UVM.

Responsibilities

• Develop verification plans with design and software teams.
• Build scalable UVM environments for block-level and full-chip verification.
• Create directed, constrained-random and random test cases to stress designs.
• Develop test harnesses, scoreboards and coverage infrastructure.
• Support verification across simulation, emulation and ASIC platforms.

Skills

SystemVerilog

SystemC

UVM

AMBA protocols

Verification planning

Education

Electrical/Computer Engineering

Tools

UVM testbenches

Simulation tools

Job description

A well-backed startup is looking to bring on a Lead Verification Engineer to build their verification architecture from the ground up. Working alongside design, architecture and physical teams, you will set technical direction for verifying complex custom silicon, grow your team and build testbenches from scratch.

The Role

• Work closely with design and software teams during microarchitecture and design reviews to develop comprehensive verification plans.
• Develop scalable UVM-based verification environments and reusable infrastructure for block-level and full-chip verification.
• Create directed, constrained-random and random test cases to thoroughly stress complex designs and identify functional issues.
• Develop test harnesses, scoreboards and coverage infrastructure to track verification progress across regressions.
• Support verification across simulation, emulation and ASIC platforms.

Experience

• 10+ years of experience verifying complex ASICs.
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or equivalent experience.
• Strong knowledge of industry-standard on-chip interconnect protocols, including AMBA
• Strong SystemVerilog/SystemC and UVM experience.
• Proven experience taking complex products through to first-pass silicon success.

We are open to speaking with candidates looking for either hybrid or remote working.