Lead Design Verification Engineer - AI Accelerator

Velaura AI, Inc.; Santa Clara, Northern (CA, KY); Hybrid; USD 200,000 - 350,000; Full time

Job summary

Velaura AI, Inc. is seeking Design Verification Engineers to verify AI acceleration units and support the development of test plans and reference models for high-performance hardware.

You will work with architects, RTL and software teams to ensure numerical correctness, performance, and energy efficiency across workloads including LLMs and vision tasks. The role emphasizes building verification environments, stimulus, and coverage, with a focus on precision, quantization, and robust bring-up

Qualifications

• 8+ years verifying high performance compute or complex digital designs.
• Understanding of LLMs including transformer structure and inference data flow.
• Knowledge of GEMM and GEMV operations and how they map onto hardware.
• Experience with SystemVerilog, UVM, C and C++, assertions and coverage driven verification.
• Experience building or using reference models in C, C++ or Python.
• Understanding of numerical formats and precision tradeoffs (FP16, BF16, FP8, INT8).
• Experience owning a block or unit through test plan to coverage closure.

Responsibilities

• Own verification of Velaura's custom AI acceleration units including matrix and vector compute engines.
• Develop test and coverage plans with architects for numerical hardware correctness.
• Build verification environments using SystemVerilog, UVM, C and C++ with portable stimulus and coverage.
• Develop reference models for GEMM and GEMV and compare against hardware results.
• Verify accelerator data flow including tiling, accumulation and writeback.
• Verify throughput, latency, and power metrics against aggressive workloads.

Job description

Velaura AI, Inc. is seeking Design Verification Engineers to verify AI acceleration units and support the development of test plans and reference models for high-performance hardware.

You will work with architects, RTL and software teams to ensure numerical correctness, performance, and energy efficiency across workloads including LLMs and vision tasks. The role emphasizes building verification environments, stimulus, and coverage, with a focus on precision, quantization, and robust bring-up