Senior ML IP Verification Engineer for AI Accelerators

Meta; Austin (TX); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta Reality Labs seeks a Design Verification Engineer to drive validation of AI accelerators and ML IPs within a multidisciplinary team. You will create robust test benches, define verification plans, and push for high-quality silicon from RTL through emulation.

Strong SystemVerilog/UVM and C/C++ verification experience are required. Join a cutting-edge group working on AR/VR hardware; collaborate across Design, Model, Emulation and Silicon teams, and help deliver state-of-the-art machine

Qualifications

• 10+ years SystemVerilog/UVM verification
• 10+ years IP/SoC verification with SystemVerilog UVM/OVM
• Experience with SV Assertions, Formal, Emulation
• Experience with EDA tools and scripting (Python, TCL, Perl, Shell) used for verification
• Bachelor's degree in CS/CE or equivalent practical experience

Responsibilities

• Develop verification methodologies for ML IPs optimized for MR and Smart Devices
• Define, track, and lead execution of detailed test plans
• Implement scalable test benches with checkers, reference models, and assertions in SystemVerilog
• Drive design verification closure using defined metrics, coverage, and tests
• Collaborate with Design, Model, Emulation and Silicon validation teams
• Support hand-off/integration of subsystems/IP into larger SOC environments
• Drive continuous DV improvements using latest verification tools and methods

Skills

SystemVerilog/UVM

C/C++ verification

IP/SoC verification

SV Assertions

Emulation

Scripting (Python/TCL/Perl/Shell)

First-pass ASIC success

Education

Bachelor's degree in CS/CE or equivalent

Master's degree in EE or CS (preferred)

Tools

Mercurial (Hg)

Git

FPGA/emulation debugging

Job description

Meta Reality Labs seeks a Design Verification Engineer to drive validation of AI accelerators and ML IPs within a multidisciplinary team. You will create robust test benches, define verification plans, and push for high-quality silicon from RTL through emulation.

Strong SystemVerilog/UVM and C/C++ verification experience are required. Join a cutting-edge group working on AR/VR hardware; collaborate across Design, Model, Emulation and Silicon teams, and help deliver state-of-the-art machine