Design Verification Engineer- AI Accelerator Lead

Velaura; Santa Clara (CA); On-site; USD 200,000 - 350,000; Full time

Job summary

Velaura is seeking a Design Verification Engineer to help verify its next‑generation Physical AI SoC focused on AI acceleration units. You will verify hardware correctness, performance, and numerical behavior from RTL blocks to full systems, collaborating with architects, RTL engineers, software teams and system teams.

The role emphasizes creating test and coverage plans, developing reference models for GEMM/GEMV, and validating data flow, precision, and performance per watt under representative

Qualifications

• 8 or more years verifying high performance compute or complex digital designs.
• High level understanding of LLMs including transformer structure and inference data flow.
• Knowledge of GEMM and GEMV operations and how they map onto hardware.
• Experience with SystemVerilog, UVM, C and C++, assertions and coverage driven verification.
• Experience building or using reference models in C, C++ or Python.
• Understanding of numerical formats and precision tradeoffs such as FP16, BF16, FP8 and INT8.
• Experience owning a block or unit of a design independently from test plan through coverage closure, including debug of complex failures.
• BS or higher in Computer Engineering, Electrical Engineering or Computer Science.

Responsibilities

• Own verification of Velaura's custom AI acceleration units including matrix and vector compute engines.
• Work with architects to understand the intent behind a newly designed microarchitecture and turn it into detailed test and coverage plans, including the criteria that define correctness for numerical hardware.
• Build verification environments using SystemVerilog, UVM, C and C++, with stimulus, checkers, assertions, trackers and coverage that stay portable across block and subsystem environments.
• Develop reference models for GEMM and GEMV operations and compare hardware results against them.
• Verify accelerator data flow including operand staging, tiling, accumulation and result writeback.
• Verify precision, rounding and quantization behavior against the architecture specification.
• Verify throughput, latency, utilization and performance per watt against aggressive targets under representative LLM and vision workloads.
• Execute regressions through design and environment bring up, track progress using bug and coverage metrics, and support emulation and pre silicon bring up with the compiler and runtime teams.

Skills

High performance compute verification

LLM/inference data flow understanding

Numerical formats and precision trade‑

Education

BS or higher in Computer Engineering, Electrical Engineering or Computer Science

Tools

SystemVerilog

UVM

C

C++

Python

Assertions & coverage

Job description

Role Overview

We are looking for talented Design Verification Engineers to help verify and deliver Velaura's next generation Physical AI SoC. You will work closely with architects, RTL engineers, software engineers and system teams to establish confidence in the correctness, performance, reliability and safety of the design, from individual RTL blocks through complete hardware and software systems running real workloads.

This role focuses on our AI acceleration units. We are designing custom compute engines from scratch to deliver industry leading inference performance at best in class energy efficiency, and every gain has to come inside a tight power envelope. You will own verification of the hardware that makes those numbers real, where correctness means numerical behavior as much as protocol.

Responsibilities

• Own verification of Velaura's custom AI acceleration units including matrix and vector compute engines.
• Work with architects to understand the intent behind a newly designed microarchitecture and turn it into detailed test and coverage plans, including the criteria that define correctness for numerical hardware.
• Build verification environments using SystemVerilog, UVM, C and C++, with stimulus, checkers, assertions, trackers and coverage that stay portable across block and subsystem environments.
• Develop reference models for GEMM and GEMV operations and compare hardware results against them.
• Verify accelerator data flow including operand staging, tiling, accumulation and result writeback.
• Verify precision, rounding and quantization behavior against the architecture specification.
• Verify throughput, latency, utilization and performance per watt against aggressive targets under representative LLM and vision workloads.
• Execute regressions through design and environment bring up, track progress using bug and coverage metrics, and support emulation and pre silicon bring up with the compiler and runtime teams.

Required Qualifications

• 8 or more years verifying high performance compute or complex digital designs.
• High level understanding of LLMs including transformer structure and inference data flow.
• Knowledge of GEMM and GEMV operations and how they map onto hardware.
• Experience with SystemVerilog, UVM, C and C++, assertions and coverage driven verification.
• Experience building or using reference models in C, C++ or Python.
• Understanding of numerical formats and precision tradeoffs such as FP16, BF16, FP8 and INT8.
• Experience owning a block or unit of a design independently from test plan through coverage closure, including debug of complex failures.
• BS or higher in Computer Engineering, Electrical Engineering or Computer Science.

Preferred Qualifications

• Prior experience porting LLM or neural network models to RTL and verifying them.
• Experience verifying a custom accelerator developed from scratch rather than an integrated third party IP.
• Familiarity with systolic arrays, tensor cores, attention, KV cache or mixture of experts hardware.
• Experience with PyTorch, ONNX or compiler and runtime stacks for accelerators.
• Experience with formal verification, gate level simulation or silicon bring up.
• Exposure to performance modeling, power analysis, profiling and workload characterization.
• Familiarity with robotics, drones, autonomous vehicles or edge AI systems.
• Experience using AI assisted verification workflows to improve productivity and coverage.

$200,000 - $350,000 a year

Compensation & Benefits

At Velaura, we believe exceptional talent deserves exceptional rewards. Compensationfor this role includes a competitive base salary, performance-based incentives, andequity participation, allowing team members to share in the company’s long-termsuccess.

Your base pay will depend on your skills, qualifications, experience, and location.

In addition to compensation, Velaura offers a comprehensive benefits package that may include medical, dental, and vision coverage; paid time off; flexible work arrangements; professional development opportunities; and other benefits designed to support the well-being and growth of our team.

Velaura is committed to pay equity and transparency and regularly benchmarks compensation to ensure we remain competitive in the market.

Why Velaura?

Velaura is building next-generation compute technology for cloud, edge, and PhysicalAI. Our solutions will enable robots, autonomous systems, drones, and other intelligentmachines to operate efficiently in the physical world.
This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape thefuture of Physical AI, we would love to hear from you.

Equal Employment Opportunity and Accommodations

Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity.Qualified applicants will receive consideration for employment without regard to race,color, religion, national origin, gender, sexual orientation, gender identity, disability orprotected veteran status. We also take affirmative action to offer employment
opportunities to minorities, women, individuals with disabilities, and protected veterans.

Velaura is committed to working with qualified individuals with physical or mentaldisabilities. Applicants who would like to contact us regarding the accessibility of ourwebsite or who need special assistance or a reasonable accommodation for any part ofthe application or hiring process may contact us at: [e-mail]. This contact
information is for accommodation requests only. Evaluation of requests for reasonableaccommodation will be determined on a case-by-case basis.