AI Accelerator Design Verification Engineer

Meta; Redmond (WA); On-site; USD 178,000 - 250,000; Full time

Job summary

Reality Labs at Meta seeks a Design Verification Engineer for AI accelerators in AR and smart devices. You will build test benches, define verification strategies, and work with researchers, architects, and silicon teams to validate state-of-the-art machine learning IPs.

Requirements include 10+ years in SystemVerilog/UVM, IP/SoC verification, SV assertions, Emulation, and scripting; a Bachelor's in CS/CE or equivalent; a Master's degree is preferred. On-site in Redmond, WA.

Qualifications

• 10+ years of SystemVerilog/UVM verification
• 10+ years of IP/sub-system/SoC verification using SystemVerilog UVM/OVM
• Experience with SV Assertions, Formal, Emulation
• Experience with EDA tools and scripting (Python, TCL, Perl, Shell)
• Track record of first-pass success in ASIC development cycles
• Bachelor's degree in CS/CE or equivalent practical experience

Responsibilities

• Develop verification methodologies for multiple ML IPs optimized for MR and smart devices
• Define, track, and lead execution of detailed test plans
• Implement scalable test benches including checkers, reference models, assertions in SystemVerilog
• Drive Design Verification to closure based on defined verification metrics
• Collaborate with Design, Model, Emulation and Silicon validation teams
• Support hand-off and integration of subsystems/IP blocks into larger SOC environments
• Drive continuous Design Verification improvements using latest verification tools and methodologies

Skills

SystemVerilog/UVM

C/C++ verification

IP/SoC verification

SV Assertions/Formal/Emulation

EDA tools scripting

ASIC development

Education

Bachelor's degree in Computer Science or Computer Engineering or equivalent

Master's degree in Electrical Engineering or Computer Science

Tools

Mercurial (Hg)

Git

Python scripting

Job description

Reality Labs at Meta seeks a Design Verification Engineer for AI accelerators in AR and smart devices. You will build test benches, define verification strategies, and work with researchers, architects, and silicon teams to validate state-of-the-art machine learning IPs.

Requirements include 10+ years in SystemVerilog/UVM, IP/SoC verification, SV assertions, Emulation, and scripting; a Bachelor's in CS/CE or equivalent; a Master's degree is preferred. On-site in Redmond, WA.