Lead Verification Engineer - ML Accelerator IP

Meta; Sunnyvale (CA); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta Reality Labs in Sunnyvale, CA seeks a Design Verification Engineer for ML accelerators. You will work with researchers and engineers to implement testing infrastructure validating core IPs and contributing to ML algorithm development and optimization.

Collaboration with design, model, emulation, and silicon validation teams is essential. Ideal candidates have 10+ years of SystemVerilog/UVM verification experience, IP/SoC verification exposure, and strong scripting with Python and TCL.

Qualifications

• 10+ years of hands-on SystemVerilog/UVM verification experience.
• 10+ years IP/SoC verification experience using SystemVerilog UVM/OVM.
• Experience in SV Assertions, Formal, Emulation.
• Experience with Python, TCL, Perl, Shell for verification tooling.
• Bachelor's degree in Computer Science, Computer Engineering, or equivalent.

Responsibilities

• Develop industry leading ML IP’s verification methodologies for mixed reality and smart devices.
• Define, track, and lead detailed test plans for modules and top levels.
• Implement scalable test benches including checkers and reference models.
• Drive verification closure based on defined metrics and coverage.
• Collaborate with Design, Model, Emulation, and Silicon validation teams.
• Support hand-off and integration of subsystems into SOC environments.
• Drive continuous verification improvements with modern methodologies and tools.

Skills

SystemVerilog/UVM

C/C++ verification

SoC verification

Python scripting

Formal

Test bench development

Education

Bachelor's degree in CS/CE or related field

Master's degree preferred

Tools

Git

Mercurial Hg

EDA tools

Python

Job description

Meta Reality Labs in Sunnyvale, CA seeks a Design Verification Engineer for ML accelerators. You will work with researchers and engineers to implement testing infrastructure validating core IPs and contributing to ML algorithm development and optimization.

Collaboration with design, model, emulation, and silicon validation teams is essential. Ideal candidates have 10+ years of SystemVerilog/UVM verification experience, IP/SoC verification exposure, and strong scripting with Python and TCL.