Lead Design Engineer

Cadence Design Systems; San Jose (CA); On-site; USD 115,000 - 213,000; Full time

Benefits offered by this job

Paid vacation

401(k) with employer match

Employee stock purchase plan

Medical/dental/vision plans

And more

Job summary

Cadence Design Systems is seeking a leader to drive electrical and functional validation for next-generation DDR interfaces (DDR5/LPDDR5/LPDDR6/HBM4/GDDR7). You will design innovative testing strategies, accelerate post-silicon bring-up, and transform data into insights through advanced analysis and visualization.

The role requires M.Tech with 4+ years or B.Tech with 6+ years experience, with strong Python automation, debugging, and cross-team collaboration across locations.

Qualifications

• Must have M.Tech with 4+ years or B.Tech with 6+ years experience.
• Experience in testing DDR interfaces (DDR5/LPDDR5/LPDDR6/HBM4/GDDR7) is preferred.
• Strong data analysis and visualization skills to turn raw data into insights.
• Proficient in Python for validation, data processing, and reporting.
• Excellent debugging and cross-team collaboration skills using JIRA.

Responsibilities

• Lead electrical and functional validation for next-generation DDR interfaces.
• Design and execute testing strategies to accelerate post-silicon bring-up.
• Transform raw data into actionable insights through analysis and visualization.
• Drive JIRA-based debug workflows to resolve complex issues.
• Deliver characterization reports that influence product decisions and customer success.
• Serve as the go-to expert for DDR IP challenges.

Skills

Python scripting

Test automation

DDR interface validation

JIRA debugging

Education

M. Tech with 4+ years experience

B. Tech with 6+ years experience

Tools

JIRA

Python

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description: Lead cutting-edge electrical and functional validation for next-generation DDR interfaces such as DDR5, LPDDR5, LPDDR6, HBM4 and GDDR7. Design and execute innovative testing strategies to accelerate post-silicon bring-up. Transform raw data into actionable insights through advanced analysis and visualization. Resolve complex issues by driving JIRA-based debug workflows and collaborating across teams. Deliver high-impact characterization reports that influence product decisions and customer success. Automate using Python for validation, data processing, and reporting. Be the go-to expert for customer DDR IP challenges, ensuring rapid debug and world-class technical support.

Experience: M. Tech + 4 years’ experience or B. Tech with 6 years’ experience.

The annual salary range for California is $114,800 to $213,200.

You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.

• paid vacation and paid holidays
• 401(k) plan with employer match
• employee stock purchase plan
• a variety of medical, dental and vision plan options
• and more

We’re doing work that matters. Help us solve what others can’t.

Cadence plays a critical role in creating the technologies that modern life depends on.

We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.

Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.