Lead DDR Validation Engineer: Bring-Up & Automation

Cadence Design Systems

San Jose (CA)

On-site

USD 115,000 - 213,000

Full time

10 days ago

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Benefits offered by this job

Paid vacation
401(k) with employer match
Employee stock purchase plan
Medical/dental/vision plans
And more

Job summary

Cadence Design Systems is seeking a leader to drive electrical and functional validation for next-generation DDR interfaces (DDR5/LPDDR5/LPDDR6/HBM4/GDDR7). You will design innovative testing strategies, accelerate post-silicon bring-up, and transform data into insights through advanced analysis and visualization.

The role requires M.Tech with 4+ years or B.Tech with 6+ years experience, with strong Python automation, debugging, and cross-team collaboration across locations.

Qualifications

  • Must have M.Tech with 4+ years or B.Tech with 6+ years experience.
  • Experience in testing DDR interfaces (DDR5/LPDDR5/LPDDR6/HBM4/GDDR7) is preferred.
  • Strong data analysis and visualization skills to turn raw data into insights.
  • Proficient in Python for validation, data processing, and reporting.
  • Excellent debugging and cross-team collaboration skills using JIRA.

Responsibilities

  • Lead electrical and functional validation for next-generation DDR interfaces.
  • Design and execute testing strategies to accelerate post-silicon bring-up.
  • Transform raw data into actionable insights through analysis and visualization.
  • Drive JIRA-based debug workflows to resolve complex issues.
  • Deliver characterization reports that influence product decisions and customer success.
  • Serve as the go-to expert for DDR IP challenges.

Skills

Python scripting
Test automation
DDR interface validation
JIRA debugging

Education

M. Tech with 4+ years experience
B. Tech with 6+ years experience

Tools

JIRA
Python

Job description

Cadence Design Systems is seeking a leader to drive electrical and functional validation for next-generation DDR interfaces (DDR5/LPDDR5/LPDDR6/HBM4/GDDR7). You will design innovative testing strategies, accelerate post-silicon bring-up, and transform data into insights through advanced analysis and visualization.

The role requires M.Tech with 4+ years or B.Tech with 6+ years experience, with strong Python automation, debugging, and cross-team collaboration across locations.

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