Interconnect Design Engineer

SiFive; Santa Clara (CA); On-site; USD 158,760 - 194,040; Full time

Benefits offered by this job

Healthcare

Retirement plans

Paid time off

Incentive compensation

Job summary

A leading technology company in California is seeking a staff level hardware engineer passionate about designing cutting-edge CPU and interconnect IP to drive RISC-V adoption. You will architect and implement advanced interconnects, enhance performance, and integrate new designs into the Chisel framework. Ideal candidates will have strong RTL design skills and a solid software engineering background, preferably with experience in bus protocols and collaboration in a team-oriented environment. Competitive pay and benefits offered.

Qualifications

• Strong software engineering background including object-oriented and functional programming.
• Ability to architect solutions to connect bus fabrics of disparate protocols.
• Experience with domain-specific languages for hardware design.

Responsibilities

• Architect and design an enhanced TileLink interconnect.
• Implement RTL generators for optimal self-configuration.
• Integrate new design content into the Chisel/FIRRTL framework.

Skills

Cache and cache coherency architectures

NoC or interconnect fabrics

Bus protocols (AXI, AHB, APB, CHI)

Software engineering skills

RTL design in Verilog/SystemVerilog/VHDL

Attention to detail

Team collaboration

Education

BS/MS in EE, CE, CS or related technical discipline

Tools

Git

GitHub

Jira

Confluence

Job description

SiFive is looking for a staff level hardware engineer who is passionate about designing industry‑leading CPU and interconnect IP to help drive the tidal wave of adoption of RISC‑V as the architecture of choice for SOC designs. We’re creating massively customizable IP and improving time‑to‑market by designing hardware as highly‑configurable generators. We leverage technology and ideas from the software industry to execute hardware design with the agility of software development.

Responsibilities

• Architect, design and implement an enhanced TileLink interconnect, cache controllers, protocol bridges, and other infrastructure/uncore logic as RTL generators in Chisel.
• Implement RTL generators such that elements self‑configure to optimally connect to each other.
• Enhance future designs to provide higher performance, more efficient multi‑core and multi‑system coherence.
• Design extensive configurability as a first‑class consideration.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements that enable automatic configuration/generation of documentation, verification testbenches, and tests.
• Perform initial sandbox verification and work with the design verification team to create and execute thorough verification test plans.
• Ensure that knowledge is shared via creation and maintenance of great documentation and participation in a culture of collaborative design.

Qualifications

• Knowledge of cache and cache coherency architectures and concepts.
• Experience with NoC or other interconnect fabrics.
• Familiarity with industry‑standard bus protocols (AXI, AHB, APB, CHI).
• Ability to architect solutions to connect bus fabrics of disparate protocols.
• Strong software engineering skills/background, including:
  • Object‑oriented, aspect‑oriented, and functional programming.
  • Templated metaprogramming in any language.
  • Compiler infrastructures, particularly for domain‑specific languages.
  • Data modeling for intermediate representations that optimize or transform compiler passes.
  • Test‑driven development and adaptive unit testing.
• Proficiency with hardware (RTL) design in Verilog, SystemVerilog, or VHDL.
• Attention to detail and a focus on high‑quality design.
• Ability to work well with others and belief that engineering is a team sport.
• BS/MS in EE, CE, CS or related technical discipline, or equivalent experience.

Nice to Have

• Experience with Scala/Chisel, Bluespec, or another DSL for expressing configurable hardware via software.
• Knowledge of RISC‑V architecture.
• Experience with Git, GitHub, Jira, Confluence.

Pay & Benefits

Base Pay Range: $158,760.00 – $194,040.00. In addition to base pay, this role may be eligible for variable or incentive compensation and/or equity. The role also includes a comprehensive benefits package, which may include healthcare, retirement plans, paid time off, and more.

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in the United States of America. Any offer is contingent on the Company verifying that you are authorized for access to export‑controlled technology under applicable export control laws or that we can obtain the required export licenses.

Equal Opportunity Employer

SiFive is an equal‑opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

As an E‑Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I‑9, Employment Eligibility Verification, upon hire. We do not use E‑Verify to pre‑screen job candidates and will comply with all E‑Verify regulations.

California residents: please see our job candidate notice for more information on how we handle your personal information and your privacy rights: Privacy Policy Document.