Lead Circuit Design Engineer, Custom ASICs

Apple; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Apple is seeking a Circuit Design Engineering Lead to guide a talented team within the Digital Design Engineering group. You will lead the design of high-performance, low-power standard cells and drive PPA improvements across CPU, SOC, and GPU integration efforts.

You will manage the development of new circuits, coordinate with foundries on iPDK requirements, and mentor a small team to deliver cutting-edge ASIC designs for market-ready products.

Qualifications

• Bachelor's degree required with 3+ years of relevant circuit design experience.
• 3+ years of standard cells circuit development experience.
• Experience leading and mentoring a small team.
• Strong influence and interpersonal skills; ability to work with multi-functional teams.
• Knowledge of standard cell layout, DRM, DRC/LVS, PDV flows, and layout rules.

Responsibilities

• Drive development of high-performance, low-power standard cells to improve design PPA.
• Develop optimal level shifters and retention designs for low-power requirements.
• Identify next-generation ideas to push PPA improvements further.
• Collaborate with CPU, SoC and GPU teams on chip-level integration requirements.
• Perform circuit QA checks and develop new methodologies for design validation.
• Coordinate with foundries on DRM-compliant layout checkers and iPDK requirements.
• Plan and drive the development of new circuits and technology node enablement.
• Manage migration to new PDK/PDV for standard cells and releases.

Skills

Standard cells dev

Circuit methodologies

Team leadership

Interpersonal skills

Layout rules PDV

Virtuoso proficiency

Power management cells

Circuit robustness analysis

Perl/TCL scripting

Education

Bachelor's degree

Tools

Virtuoso

Job description

Apple is seeking a Circuit Design Engineering Lead to guide a talented team within the Digital Design Engineering group. You will lead the design of high-performance, low-power standard cells and drive PPA improvements across CPU, SOC, and GPU integration efforts.

You will manage the development of new circuits, coordinate with foundries on iPDK requirements, and mentor a small team to deliver cutting-edge ASIC designs for market-ready products.