Lead Circuit Design Engineer - Custom ASICs

Apple Inc.; Beaverton (OR); On-site; USD 120,000 - 190,000; Full time

Job summary

Apple Inc. in Beaverton, OR is seeking a Circuit Design Engineering Lead to drive development of high performance, low power standard cells and contribute to chip-level integration for SOC designs.

You will lead a small, multi-disciplinary team, collaborate with CPU/SOC/GPU teams, manage PDV/DRM checks, and migrate designs to new PDKs while delivering robust, market-ready IP on aggressive timelines. This role demands strong influence, mentoring, and hands-on optimization of PPA to ensure design

Qualifications

• 3+ years of experience in Standard cells circuit development.
• Proven experience leading & mentoring a small team.
• Strong influence and interpersonal skills; able to work with multi-functional teams.
• Knowledge of standard cell layout, DRM, DRC/LVS decks, PDV flows, Virtuoso.
• Design experience in advanced tech node device behavior with layout rule understanding.
• Knowledge of circuit robustness analysis.
• Experience scripting in Perl and/or TCL.

Responsibilities

• Drive development of high performance, low power optimized standard cells to improve design PPA.
• Drive development of optimal level shifters, retention designs, etc that cater to today’s Low Power Design Requirements.
• Identify next generation ideas to drive PPA improvements.
• Engage with CPU, SOC and GPU teams on chip level integration requirements.
• Drive Circuit QA checks & analysis, develop new methodologies based on new design requirements.
• Work with foundries on DRM compliant layout checkers and iPDK requirements.
• Plan & drive development of designs like new circuits & tech node enablement.
• Manage migration to new PDK, PDV of standard cells & releases.

Skills

Standard cells circuit development

Mentoring a small team

Interpersonal skills

Cross-functional collaboration

PDV flows

Education

Bachelor's Degree

Tools

Virtuoso

Job description

Apple Inc. in Beaverton, OR is seeking a Circuit Design Engineering Lead to drive development of high performance, low power standard cells and contribute to chip-level integration for SOC designs.

You will lead a small, multi-disciplinary team, collaborate with CPU/SOC/GPU teams, manage PDV/DRM checks, and migrate designs to new PDKs while delivering robust, market-ready IP on aggressive timelines. This role demands strong influence, mentoring, and hands-on optimization of PPA to ensure design