ASIC Circuit Design Engineer – Low-Power & ML Accel

Apple Inc.; Santa Clara, Northern (CA, KY); Hybrid; USD 145,000 - 218,000; Full time

Benefits offered by this job

Medical and dental coverage

Retirement benefits

Employee stock programs

Tuition reimbursement

Relocation assistance

Job summary

Apple Inc. in Santa Clara, CA is seeking engineers to design advanced custom circuits for high-performance silicon in an ASIC/soc context.

You will work on power-efficient circuits, collaborate across power, PD, and architecture teams, and verify designs from schematic to silicon bring-up. The role emphasizes deep submicron device physics, process corners, and tight integration with layout teams, with potential exposure to ML accelerators and on-chip sensors.

Qualifications

• Experience in design of low voltage custom circuits circuit
• Good understanding of deep submicron device physics, leakage mechanisms, technology interactions with device behavior
• Proficiency in scripting languages (Python / Perl or others) and CAD automation tools.
• Knowledge of industry standard circuit simulation and design tools

Responsibilities

• Develop custom circuits to improve chip power efficiency.
• Collaborate with power team, PD and architects to define specifications and requirements.
• Perform design, analysis, modeling/simulation, circuit level specifications, schematic capture, spice simulation / margin verification across PVT, statistical design, functional verification and silicon bring up.
• Work closely with layout team to complete the design and oversee the layout quality.
• Develop / drive circuit methodology to achieve the highest design quality metrics.

Job description

Apple Inc. in Santa Clara, CA is seeking engineers to design advanced custom circuits for high-performance silicon in an ASIC/soc context.

You will work on power-efficient circuits, collaborate across power, PD, and architecture teams, and verify designs from schematic to silicon bring-up. The role emphasizes deep submicron device physics, process corners, and tight integration with layout teams, with potential exposure to ML accelerators and on-chip sensors.