Lead ASIC Verification Engineer - UVM/SystemVerilog

Mirafra Technologies; California (MO); On-site; USD 120,000 - 180,000; Full time

Job summary

Mirafra Technologies is seeking an experienced verification Engineer to architect block and full-chip verification environments using HVLs and constrained random methods for SOCs with embedded CPUs and mixed-signal interfaces. The role requires UVM, SystemVerilog, and SVA expertise to drive test plans, coverage metrics, and bug replication in simulation.

Responsibilities include debugging RTL/gate simulations with design teams, writing diagnostics for FPGA prototype validation and ASIC, and

Qualifications

• HVLs and constrained random techniques for SOC verification.
• Develop test plans and coverage metrics from specifications and write tests in C, SV, UVM.
• Debug RTL and gate simulations with design engineers to verify fixes.
• Write diagnostics for FPGA prototype validation (pre-tapeout) and ASIC.
• Replicate silicon bugs in simulation environments and validate fixes or SW workarounds.
• Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup.
• Evaluate verification methodologies and develop automation scripts.

Responsibilities

• Write block and chip-level tests in C, SV, UVM.
• Debug RTL and gate simulations and coordinate with design engineers.
• Create diagnostics for FPGA prototype validation and ASIC.
• Replicate silicon bugs in simulators and validate fixes or workarounds.
• Automate verification using scripts and test-pattern conversions.

Skills

HVLs

Constrained random

UVM

SystemVerilog

SVA

C

Tools

RTL debugging

Job description

Mirafra Technologies is seeking an experienced verification Engineer to architect block and full-chip verification environments using HVLs and constrained random methods for SOCs with embedded CPUs and mixed-signal interfaces. The role requires UVM, SystemVerilog, and SVA expertise to drive test plans, coverage metrics, and bug replication in simulation.

Responsibilities include debugging RTL/gate simulations with design teams, writing diagnostics for FPGA prototype validation and ASIC, and