Formal Verification Engineer: ASIC & SystemVerilog

Mirafra Technology; San Diego (CA); On-site; USD 90,000 - 120,000; Full time

Job summary

Mirafra Technology, located in San Diego, California, seeks a skilled engineer with experience in ASIC design processes and formal verification. The role requires proficiency in various design languages including VHDL, Verilog, and System Verilog.

The ideal candidate will also have familiarity with programming languages like C and C++, along with scripting skills in Unix/Linux. Join our growing team in a dynamic environment.

Qualifications

• Experience with ASIC design processes and verification tools is crucial.
• Familiarity with programming and scripting languages is required.
• Proven experience in Formal Verification is essential.

Skills

ASIC design process

Digital design

Verification tools

Computer architecture

VHDL

Verilog

System Verilog

Formal Verification

C

C++

SystemC

Unix/Linux shell programming

Perl

Java

XML

Makefile

Tools

VCS

IUS

ModelSim

Jasper

0-in

IFV

OneSpin

SLEC

Job description

Mirafra Technology, located in San Diego, California, seeks a skilled engineer with experience in ASIC design processes and formal verification. The role requires proficiency in various design languages including VHDL, Verilog, and System Verilog.

The ideal candidate will also have familiarity with programming languages like C and C++, along with scripting skills in Unix/Linux. Join our growing team in a dynamic environment.