Senior Verification Engineer, ASIC/SoC, UVM & Coverage

Lumilens Inc.; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Lumilens Inc. is seeking an experienced ASIC/SoC verification engineer to verify blocks of a first-of-its-kind chiplet.

You will build UVM testbenches, write directed and constrained-random tests, and drive functional coverage to closure across simulation and emulation environments. You will verify mixed-signal and digital blocks against golden models, integrate VIPs, and support hardware-assisted verification on emulation or FPGA prototyping.

Qualifications

• BS or MS in Electrical/Computer Engineering or equivalent experience.
• 3+ years of ASIC/SoC functional verification.
• Strong UVM/SystemVerilog proficiency with constrained-random and coverage-driven verification.
• Testbench development and coverage closure experience.
• Strong debugging skills across simulation and scripting in Python, Perl, or TCL.
• Familiarity with regression/CI flows and failure triage.

Responsibilities

• Build and extend UVM testbenches (agents, sequences, scoreboards) for assigned blocks and subsystems.
• Write directed and constrained-random tests; develop functional coverage and drive to closure.
• Verify in-house engines against a golden model with programmable error injection and coverage.
• Integrate and use VIPs (UCIe, PCIe/CXL) and run compliance, link-training, and lane-repair scenarios.
• Run regressions, triage failures, and maintain the CI/regression flow.
• Register (UVM RAL) verification, firmware co-simulation, and boot flows on MCU subsystems.
• Mixed-signal co-simulation; verify digital blocks against analog/mixed-number models.
• Support hardware-assisted verification through emulation/FPGA prototyping.
• Participate in gate-level and low-power (UPF) verification during signoff.
• Collaborate with design, architecture, modeling, and DFT teams as blocks progress.

Skills

UVM/SystemVerilog

Testbench development

Coverage closure

Regression/CI flows

Python/Perl/TCL scripting

Debugging across simulation

ASIC/SoC verification

Education

BS or MS in Electrical/Computer Engineering

Tools

UCIe VIP

PCIe/CXL VIP

Emulation (Palladium/Veloce)

FPGA Prototyping (HAPS/Protium)

Job description

Lumilens Inc. is seeking an experienced ASIC/SoC verification engineer to verify blocks of a first-of-its-kind chiplet.

You will build UVM testbenches, write directed and constrained-random tests, and drive functional coverage to closure across simulation and emulation environments. You will verify mixed-signal and digital blocks against golden models, integrate VIPs, and support hardware-assisted verification on emulation or FPGA prototyping.