Lead ASIC DFT Staff Engineer

Coelate Technologies; United States; On-site; USD 140,000 - 190,000; Full time

Job summary

Coelate Technologies is seeking an experienced ASIC DFT engineer to own end-to-end DFT implementation across large SoCs. You will apply scan architectures, ATPG, MBIST, LBIST, and JTAG techniques, ensuring robust test coverage and efficient post-silicon debug.

The role requires hands-on experience with Synopsys, Cadence, and Siemens/Mentor tools, along with strong communication skills and independent work capability in a fast-paced environment.

Qualifications

• Hands-on ASIC DFT implementation and end-to-end ownership.
• Deep knowledge of DFT fundamentals, fault models, test techniques, and coverage concepts.
• Scan architecture expertise, ATPG, MBIST, LBIST, and JTAG/boundary scan.

Responsibilities

• Own end-to-end DFT for complex ASICs/SoCs.
• Apply scan architectures, ATPG setup, simulation, and debug.
• Perform MBIST/LBIST verification and DRC analysis.
• Collaborate with RTL, physical design, and validation teams.
• Drive test coverage and post-silicon bring-up efforts.

Skills

ASIC DFT

ATPG/MBIST/LBIST

Scan architecture

JTAG & boundary scan

Silicon debug

EDA tools (Synopsys Cadence Mentor)

Test coverage

Post-silicon debug

RTL/PLL concepts

SoC DFT flows

Tools

Synopsys

Cadence

Siemens/Mentor

Tessent/SSN

Job description

• Strong hands-on experience in ASIC DFT with end-to-end ownership.
• Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
• Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
• Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
• Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
• Experience with MBIST implementation and verification; SMS experience preferred.
• Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
• Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
• Proven post-silicon debug and silicon bring-up experience.
• Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
• Strong communication skills and the ability to work independently with minimal ramp-up.