Lead AI Silicon Verification Architect (UVM/SystemVerilog)

Unconventional, Inc.; United States; Remote; USD 140,000 - 210,000; Full time

Benefits offered by this job

Health benefits

401k matching

Unlimited PTO

Complimentary meals in Palo Alto

Job summary

Unconventional, Inc. is seeking a senior Verification Engineer to define and own verification strategy for IP blocks and full chip tape-out in a fast-moving AI hardware startup.

You will architect scalable testbenches using UVM and SystemVerilog, own verification closures, collaborate with design and software teams, and optimize CI automation on Linux with Cadence and Synopsys tools in a Palo Alto environment.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 8+ years hands-on experience with advanced verification methodologies and languages (UVM, SystemVerilog).
• Proven track record developing and maintaining complex verification testbenches and automated test environments.
• Proficiency in scripting for automation of verification flows and result analysis (Python, Shell, Bash).
• Familiarity with Linux andCadence/Synopsys toolchains.

Responsibilities

• Define, architect, and implement verification plans and environments for IP blocks and full chip from specification to tape-out.
• Help build verification infrastructure that is flexible and scalable for growth.
• Take full ownership of the verification lifecycle, including scalable testbenches, test cases, and verification environments.
• Deploy industry-standard methodologies (UVM/SystemVerilog) for constrained-random stimulus, coverage-driven verification, and assertions.
• Collaborate with digital/analog design, software, and systems teams to define verification requirements and debug hardware/software interactions.
• Perform exhaustive analysis of functional and code coverage; debug RTL/gate-level failures to ensure 100% verification closure.

Skills

UVM

SystemVerilog

Testbench design

Automation scripting

Linux tooling

Cadence/Synopsys tools

Education

Bachelor's degree in Electrical/Computer Engineering or Computer Science

Tools

Cadence

Synopsys

Linux

Python

Shell/Bash

Job description

Unconventional, Inc. is seeking a senior Verification Engineer to define and own verification strategy for IP blocks and full chip tape-out in a fast-moving AI hardware startup.

You will architect scalable testbenches using UVM and SystemVerilog, own verification closures, collaborate with design and software teams, and optimize CI automation on Linux with Cadence and Synopsys tools in a Palo Alto environment.