Lead Design Verification Engineer

Oho Group; Austin (TX); Hybrid; USD 180,000 - 260,000; Full time

Job summary

Oho Group is seeking a Lead Verification Engineer to build their verification architecture from the ground up. You will set technical direction for verifying complex custom silicon and drive the verification strategy across design, architecture and physical teams.

The role includes growing the team, creating testbenches from scratch, and delivering first-pass silicon success across simulation, emulation and ASIC platforms. Hybrid or remote-friendly, Austin-area based.

Qualifications

• 10+ years of experience verifying complex ASICs.
• Bachelor's or Master's in EE/CE or equivalent.
• Strong knowledge of AMBA on-chip interconnects.
• Proficient in SystemVerilog, SystemC and UVM.
• Track record of achieving first-pass silicon success.

Responsibilities

• Develop verification plans with design and software teams.
• Develop scalable UVM-based verification environments and reusable infrastructure for block-level and full-chip verification.
• Create directed, constrained-random and random test cases to stress complex designs.
• Develop test harnesses, scoreboards and coverage infrastructure to track progress.
• Support verification across simulation, emulation and ASIC platforms.

Skills

ASIC verification

Verification planning

Constrained-random testing

UVM

SystemVerilog

SystemC

AMBA protocols

Education

Bachelor's degree in Electrical or Computer Engineering

Master's degree (preferred)

Tools

UVM

SystemVerilog

SystemC

Emulation platforms

Job description

A well-backed startup is looking to bring on a Lead Verification Engineer to build their verification architecture from the ground up. Working alongside design, architecture and physical teams, you will set technical direction for verifying complex custom silicon, grow your team and build testbenches from scratch.

The Role

• Work closely with design and software teams during microarchitecture and design reviews to develop comprehensive verification plans.
• Develop scalable UVM-based verification environments and reusable infrastructure for block-level and full-chip verification.
• Create directed, constrained-random and random test cases to thoroughly stress complex designs and identify functional issues.
• Develop test harnesses, scoreboards and coverage infrastructure to track verification progress across regressions.
• Support verification across simulation, emulation and ASIC platforms.

Experience

• 10+ years of experience verifying complex ASICs.
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or equivalent experience.
• Strong knowledge of industry-standard on-chip interconnect protocols, including AMBA
• Strong SystemVerilog/SystemC and UVM experience.
• Proven experience taking complex products through to first-pass silicon success.

We are open to speaking with candidates looking for either hybrid or remote working.