GenAI Silicon Verification Engineer (Block-to-Tapeout)

Platform Recruitment; San Francisco (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Platform Recruitment collaborates with a high-growth AI silicon startup to recruit verification engineers. The role spans from block to system-level validation, driving testbenches and artifacts needed to close coverage.

You will lead verification at the subsystem and chip level, shape the methodology, and drive reviews toward milestones such as design freeze and tapeout. The ideal candidate has concept-to-silicon experience and strong SystemVerilog, Python and C/C++ skills, with UVM, formal

Qualifications

• Concept-to-silicon experience: from architecture/design spec through production silicon
• Proficiency in SystemVerilog, Python and C/C++ for verification and silicon modelling
• Experience with UVM and assertion-based verification; comfortable with formal and simulation-based methods
• Experience building portable tests and drivers for silicon validation and post-silicon debug
• Strong grasp of micro-architecture and high-performance compute, memory management and high-speed connectivity

Responsibilities

• Shape the verification methodology across block, subsystem, full-chip and system-level validation
• Own verification execution at subsystem and chip level; build testbenches, tests and artifacts to close coverage
• Plan and drive verification reviews (test plans, progress, closure) toward milestones including tapeout
• Translate architecture and design specifications into production silicon

Skills

Verification

Test planning

Debugging

Tools

SystemVerilog

Python

C/C++

UVM

Formal methods

Simulation

Job description

Platform Recruitment collaborates with a high-growth AI silicon startup to recruit verification engineers. The role spans from block to system-level validation, driving testbenches and artifacts needed to close coverage.

You will lead verification at the subsystem and chip level, shape the methodology, and drive reviews toward milestones such as design freeze and tapeout. The ideal candidate has concept-to-silicon experience and strong SystemVerilog, Python and C/C++ skills, with UVM, formal