Lead Advanced Packaging Engineer - Optical Chips & 2.5D/3D

Astera Labs; San Jose (CA); On-site; USD 205,000 - 260,000; Full time

Benefits offered by this job

Discretionary bonus

Benefits

Job summary

Astera Labs in San Jose, CA seeks a Principal Advanced Packaging Engineer to lead R&D for next-generation packaging technologies for optical chips. This senior individual contributor role sets technical direction and drives packaging development for NPO and CPO products.

You will define packaging flows (2.1D/2.5D/3D), qualify materials, collaborate with OSATs and suppliers, and improve yield and reliability across wafer-, panel-, and die-level processes.

Qualifications

• B.S., M.S., or Ph.D. in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field.
• 8+ years of experience in semiconductor or advanced packaging engineering with demonstrated technical leadership.
• Deep expertise in advanced packaging processes including 2.5D/3D integration, flip-chip, hybrid bonding, Cu pillar, TSV, RDL, and overmold across wafer-, panel-, and die-level flows.
• Experience with silicon photonics chip packaging and EIC/PIC integration.
• Hands-on experience with packaging materials such as underfill, molding compounds, dielectrics, adhesives, or optical-grade encapsulants.
• Proven track record of equipment and process qualification with OSAT or tool suppliers.
• Experience with PDK development and packaging design rule authoring.
• Strong foundation in yield analysis, reliability characterization, and process capability methodologies such as CpK and SPC.

Responsibilities

• Lead R&D for advanced packaging of optical chips, including 2.1D, 2.5D, and 3D integration.
• Define and optimize wafer-level, panel-level, or die-level packaging process flows.
• Drive EIC-to-PIC integration and broader optical device integration efforts.
• Select and qualify packaging materials for advanced packaging.
• Partner with OSAT, tool vendors, and material suppliers to drive equipment, process, and materials development.
• Characterize and continuously improve yield, reliability, and process capability for NPO and CPO packages.
• Develop and maintain packaging PDKs and design rules for NPO and CPO products.

Education

Electrical/Materials/Mechanical Engineering degree

Job description

Astera Labs in San Jose, CA seeks a Principal Advanced Packaging Engineer to lead R&D for next-generation packaging technologies for optical chips. This senior individual contributor role sets technical direction and drives packaging development for NPO and CPO products.

You will define packaging flows (2.1D/2.5D/3D), qualify materials, collaborate with OSATs and suppliers, and improve yield and reliability across wafer-, panel-, and die-level processes.