Junior VLSI Verification Engineer: Shape Next-Gen Chips

proteanTecs; United States; On-site; USD 90,000 - 120,000; Full time

Job summary

proteanTecs is seeking a Junior VLSI Verification Engineer to join our team in the US. You will contribute to on-chip health monitoring and verification of IP blocks, collaborating with design and software teams on ambitious projects.

Ideal candidates have a BSc in EE/CS and 1–2 years of VLSI verification, with hands-on SystemVerilog and UVM knowledge, plus familiarity with simulation tools and code coverage concepts. You’ll grow your skills in a fast-paced startup environment.

Qualifications

• BS degree in EE/CS or related field is required.
• 1–2 years in VLSI verification.
• Experience with SystemVerilog/UVM and basic digital design concepts.

Responsibilities

• Develop, debug, and maintain verification environments and testbenches.
• Analyze simulation results and waveforms to root-cause issues.
• Define and track code and functional coverage; drive closure.
• Verify IP blocks end-to-end from test planning to sign-off.
• Collaborate with design team to clarify specs and confirm completeness.
• Participate in code reviews and knowledge sharing to improve practices.

Skills

SystemVerilog

UVM

RTL design

Testbench architecture

Simulation flow

Python

Git

VCS

Questa

Xcelium

Code coverage

AXI/APB/I2C/SPI

Education

B.Sc. in Electrical/Computer Engineering

B.Sc. in Computer Science

Related field

Tools

VCS

Xcelium

Questa

Job description

proteanTecs is seeking a Junior VLSI Verification Engineer to join our team in the US. You will contribute to on-chip health monitoring and verification of IP blocks, collaborating with design and software teams on ambitious projects.

Ideal candidates have a BSc in EE/CS and 1–2 years of VLSI verification, with hands-on SystemVerilog and UVM knowledge, plus familiarity with simulation tools and code coverage concepts. You’ll grow your skills in a fast-paced startup environment.