DV - Digital Verification Engineer (Senior levels - Staff +)

Eliyan Corporation; San Francisco (CA); On-site; USD 180,000 - 260,000; Full time

Benefits offered by this job

Excellent benefits

Fun work environment

Job summary

Eliyan Corporation, a leading chiplet startup in San Francisco, seeks a staff digital verification engineer to develop state‑of‑the‑art testbenches for high‑speed IPs and chiplets. You will lead verification efforts, drive CI/CD‑aligned regression, and collaborate across design and engineering teams in a fast‑paced environment.

The role emphasizes SystemVerilog/UVM expert performance, Ethernet 802.3 compliance, and a startup mindset with a passion for innovation and quality.

Qualifications

• Masters or Ph.D in Electrical Engineering with 6+ years of experience.
• Hands-on verification of serial transmission protocols (Ethernet 100G/200G/400G/800G).
• Strong expertise in UVM, SystemVerilog test environments and assertions.
• Experience with 3rd party tools for regression management and coverage analysis.
• Experience verifying Ethernet 802.3 clauses related to high-speed standards (100G+).
• Knowledge of DRAM Controllers/PHYs and HBM memory is a plus.
• Startup mindset with cross-functional collaboration.

Responsibilities

• Develop and execute verification plans for connectivity IPs and Chiplets.
• Create and maintain SystemVerilog/UVM-based verification environments.
• Write and debug SystemVerilog/UVM compliant test cases for block and chip level.
• Maintain a regression environment enabling design CI/CD pipelines.
• Collaborate with design engineers to ensure design quality with continuous microarchitecture, test‑plan, and coverage reviews.
• Develop, maintain, and track various test plan items and progress towards RTL freeze.
• Stay up to date with industry trends, emerging technologies and standards bodies.
• Ensure IP compliance with Ethernet standards (IEEE 802.3).
• Integration 3rd party VIPs and coordinate feature/bug tracking requests.
• Perform in the capacity of a technical leader for junior verification engineers.
• Create, improve, maintain DPI based FW simulation environments.
• Create, improve, maintain GLS environments for functional and power simulations.

Skills

SystemVerilog

UVM

Testbench development

Regression tools

Ethernet 802.3 knowledge

Python scripting

Education

Master’s or PhD in Electrical Engineering

Job description

Join the leading chiplet startup! As an Eliyan staff digital verification engineer, you will be working at a fast‑paced early‑stage startup creating technologies that fuel tomorrow’s chiplet based systems with best‑in‑class power, area, manufacturability, and design flexibility. You will be developing state‑of‑the‑art testbenches and unit/chip level test cases for best‑in‑class PHYs and Controllers. You will work with a cross‑functional team of experts that operate from first principles, innovate and push the envelope to create high‑volume and high‑performance manufacturable products. We offer a fun work environment with excellent benefits.

Key Responsibilities

• Develop and execute verification plans for connectivity IPs and Chiplets
• Create and maintain SystemVerilog/UVM‑based verification environments
• Write and debug SystemVerilog/UVM compliant test cases for block and chip level
• Maintain a regression environment for enabling design CI/CD pipelines
• Collaborate with design engineers to ensure design quality with continuous microarchitecture, test‑plan, and coverage reviews
• Develop, maintain, and track various test plan items and progress towards RTL freeze
• Stay up to date with industry trends, emerging technologies and progress in standards’ bodies
• Ensure IP compliance with Ethernet standards (IEEE 802.3)
• Integration 3rd party VIPs and coordinate feature/bug tracking requests
• Perform in the capacity of a technical leader for junior verification engineers
• Create, improve, maintain DPI based FW simulation environments
• Create, improve, maintain GLS environments for functional and power simulations

Qualifications

• Masters or Ph.D in Electrical Engineering and related fields with 6+ years of experience
• Hands on experience in verification of serial transmission protocols and products (preferably in retimer, gearbox, Ethernet PMA/PCS logic)
• Strong expertise in UVM, test environment and assertion coding with SystemVerilog
• Proficiency in 3 rd party tools for regression management and coverage analysis
• 3+ experience working on Ethernet 802.3 standards’ clauses related to 100G, 200G, 400G, 800G; Auto‑Negotiation and Link Training
• Knowledge of DRAM Controllers/PHYs and HBM Memory a plus
• Strong bias for innovations across all aspects of digital verification including automation of mundane activities and methods for quality improvement
• Experience in verifying 3 rd party mixed signal IPs as well as integration of VIPs
• Proven track record of being part of a start‑up like environment

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.