Design Verification Engineer

BayOne Solutions; Carlsbad (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

BayOne Solutions is seeking a collaborative Design Verification Engineer with 5-12 years of industry experience to help create top-tier SoC verification strategies and test environments. You will participate in architectural decisions and verification planning to ensure first-time-right delivery.

Responsibilities include UVM-based environments, block- and system-level plans, and debug leadership. A strong background in SystemVerilog and high-speed interfaces is preferred for influencing silicon

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• Experience in UVM-based verification environments and testbench development.
• Proficiency in SystemVerilog and ASIC/SoC verification.
• Experience creating verification plans and debug of complex issues.
• Familiarity with Python or Perl for automation and scripts.
• Knowledge of high-speed protocols (UCIe, PCIe) preferred.

Responsibilities

• Develop and implement UVM-based verification environments.
• Create verification plans at block and system levels.
• Design verification components including assertions, traffic generators, agents, and scoreboards.
• Collaborate with cross-functional teams to evaluate testability and verification requirements.
• Lead debug efforts and provide solutions for complex technical challenges.

Skills

UVM verification

SystemVerilog

ASIC/SoC verification

Verification test plans

Debug complex issues

C for firmware bringup

Python

Perl

UCIe/PCIe protocols

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical/Communications Engineering

Tools

SystemVerilog

Python

Perl

Formal verification tools

Job description

Join our innovative team developing next-generation silicon solutions for silicon one group. We are seeking a collaborative Design Verification Engineer with 5-12 years of industry experience to help create cutting edge System-on-Chip (SoC) designs delivered first time right. You will work in a collaborative environment, participating in architectural decisions and verification strategies that directly impact product success. Our team values diverse perspectives and creative problem-solving approaches to deliver exceptional customer experiences.

Key Job Responsibilities:

• Develop and implement Universal Verification Methodology (UVM) based verification environments.
• Create comprehensive verification plans at both block and system levels.
• Design and implement verification components including assertions, traffic generators, agents, and scoreboards.
• Collaborate with cross-functional teams to evaluate design testability and verification requirements.
• Lead debug efforts and provide solutions for complex technical challenges.
• Basic Qualifications
• Bachelor's degree in Electrical Engineering or a related field.
• UVM Based testbench development.
• Experience in ASIC or SOC verification.
• Demonstrated experience in developing test plans and verification infrastructure.
• Practical knowledge of verification methodologies from block level to system level.
• Proficiency in System Verilog.
• Experience in identifying and resolving complex design and verification issues.
• Timing and gate level simulation experience.
• C coding for firmware delivery for post silicon bringup Preferred Qualifications
• Bachelors/master's degree in electrical or communications engineering or a related field.
• Experience with formal verification techniques including abstraction and end-to-end checking.
• Experience with industry-standard tools and scripting languages (Python or Perl) for automation.
• System Verilog coding and debug.
• AI based CAD efficiency improvisation initiatives High speed serial protocols preferred UCIe, PCIE etc.
• Analog debug experience including DAC/ADC & calibrations white-box verification.