Junior RTL/ASIC Verification Engineer – UVM & Automation

Amazon Inc.; Sunnyvale (CA); On-site; USD 132,000 - 185,000; Full time

Job summary

Amazon Leo is seeking a Junior Design Verification Engineer to build and maintain a verification environment for RTL against reference Matlab and system models. The role includes creating test plans, running regressions, collecting coverage, and reporting progress to the program team.

The candidate will verify ASIC implementations in Verilog/SystemVerilog, work with design and comms teams, and help automate regression workflows to support builds and data organization.

Qualifications

• Bachelor's degree in Electrical or Communications Engineering or a related field.
• 2+ years in verification, preferably in communication systems.
• 2+ years in UVM.

Responsibilities

• Implement a state of the art verification environment to test RTL against Matlab/ C models.
• Develop detailed test plans and write tests, run regressions, collect coverage matrices, and report progress.

Skills

Verification

Verification methodology

Education

Bachelor's degree in Electrical or Communications Engineering or related field

Tools

Verilog/SystemVerilog

UVM

Matlab

Job description

Amazon Leo is seeking a Junior Design Verification Engineer to build and maintain a verification environment for RTL against reference Matlab and system models. The role includes creating test plans, running regressions, collecting coverage, and reporting progress to the program team.

The candidate will verify ASIC implementations in Verilog/SystemVerilog, work with design and comms teams, and help automate regression workflows to support builds and data organization.