Junior ASIC Verification Engineer for Leo Satellite Tech

Amazon Inc.; California; On-site; USD 123,000 - 185,000; Full time

Job summary

Amazon is seeking a Junior ASIC Design Verification Engineer for the Amazon Leo program to define and implement verification environments for cutting-edge SOCs used in satellite communications. You will work with RTL, Matlab models, and embedded C/C++ test code to validate designs across FPGA and emulation platforms.

The role emphasizes formal verification techniques, UVM-based test benches, and automated regressions to maintain build integrity and test coverage across complex digital blocks.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or Electrical Engineering.
• 2+ years in verification preferably in communication systems.
• 1+ years in UVM, C/C++ and scripting.

Responsibilities

• Implement a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models.
• Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program.
• Write tests in C/C++ to execute on embedded CPU.
• Develop tests for FPGA and emulation platforms.
• Run formal verification of complex blocks to ensure functional correctness.
• Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM, System C and DPI-C.
• Develop a highly automated environment to run regressions that can be used to make builds and maintain organization of the database.

Skills

UVM

C/C++

Scripting

Education

Bachelor's degree in Computer Science, Computer Engineering, or Electrical Engineering

Tools

Matlab

Formal verification

Job description

Amazon is seeking a Junior ASIC Design Verification Engineer for the Amazon Leo program to define and implement verification environments for cutting-edge SOCs used in satellite communications. You will work with RTL, Matlab models, and embedded C/C++ test code to validate designs across FPGA and emulation platforms.

The role emphasizes formal verification techniques, UVM-based test benches, and automated regressions to maintain build integrity and test coverage across complex digital blocks.