Digital ASIC Verification Engineer - RTL, UVM & Testbenches

SpaceX; Palo Alto (CA); On-site; USD 90,000 - 130,000; Full time

Job summary

SpaceX is seeking a Design Verification Engineer (Silicon Engineering) to verify digital ASICs at block and system levels, develop testbenches, and drive pre‑ and post‑silicon validation. You will implement UVM or non‑UVM test environments, automate tests with Python and MATLAB, and contribute to chip bring‑up and verification cycles.

The role requires a Bachelor's in EE/CS/CE and 1+ years of design verification and test bench development, with strong coding skills and willingness to work in a

Qualifications

• Bachelor's in EE/CS/CE.
• 1+ years of design verification and test bench development with strong coding skills.

Responsibilities

• Verify digital ASICs at block and system levels.
• Develop testbenches and drive pre- and post-silicon validation.
• Implement UVM or non-UVM test environments.
• Automate tests with Python and MATLAB.
• Contribute to chip bring-up and verification cycles.

Skills

Testbench development

UVM environments

Coding skills

Education

Bachelor's in EE/CS/CE

Tools

Python

MATLAB

SystemVerilog

Job description

SpaceX is seeking a Design Verification Engineer (Silicon Engineering) to verify digital ASICs at block and system levels, develop testbenches, and drive pre‑ and post‑silicon validation. You will implement UVM or non‑UVM test environments, automate tests with Python and MATLAB, and contribute to chip bring‑up and verification cycles.

The role requires a Bachelor's in EE/CS/CE and 1+ years of design verification and test bench development, with strong coding skills and willingness to work in a