Junior Verification Engineer, Wireless SOCs for LEO Satcom

Amazon Inc.

Austin (TX)

In loco

USD 115.000 - 160.000

Tempo pieno

2 giorni fa
Candidati tra i primi

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Descrizione del lavoro

Amazon Leo is seeking a Junior Design Verification Engineer to help define and implement digital chip SOC verification for LEO satellite communications. You will contribute to RTL testing, test bench development, and regression planning in a fast-paced hardware team.

You will collaborate with ASIC teams to validate Verilog/SystemVerilog designs, UVM based environments, and Matlab models, while supporting automated regression and coverage reporting.

Competenze

  • Bachelor's degree in Electrical or Communications Engineering or related field.
  • 2+ years in verification, preferably in communication systems.
  • 2+ years in UVM.

Mansioni

  • Implement a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models.
  • Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program.
  • Participate in the validation of ASIC implementations in Verilog/SystemVerilog.
  • Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM.
  • Develop a highly automated environment to run regressions that can be used to make builds and maintain organization of the database.

Conoscenze

Verification experience
Strong communication skills

Formazione

Bachelor's degree in Electrical or Communications Engineering or related field
Master's or Ph.D degree in Electrical / Communications Engineering

Strumenti

MATLAB
Verilog/SystemVerilog
UVM

Descrizione del lavoro

Amazon Leo is seeking a Junior Design Verification Engineer to help define and implement digital chip SOC verification for LEO satellite communications. You will contribute to RTL testing, test bench development, and regression planning in a fast-paced hardware team.

You will collaborate with ASIC teams to validate Verilog/SystemVerilog designs, UVM based environments, and Matlab models, while supporting automated regression and coverage reporting.

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