Junior ASIC Verification Engineer (SystemVerilog/UVM)

Cisco Systems, Inc; San Jose (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Cisco Systems, Inc is seeking an ASIC Engineer to play a critical role in developing Cisco’s data center solutions. You will collaborate with verification engineers, designers, hardware, and other cross-functional teams to verify the ASIC in simulation, emulation, and bring-up to ensure seamless integration and optimal performance of Cisco’s hardware platforms.

You will maintain DV environments, construct test benches, write test plans, debug regressions, and drive verification closure, while

Qualifications

• Bachelor's degree completed within the past 3 years or expected to be completed within the next 12 months.
• Qualifying education and work experience should be in ASIC Design, Design Verification, or a related field.
• Qualifying education and work experience should be in ASIC Engineering, Verification or a related field.

Responsibilities

• Maintaining existing DV environments and enhancing them
• Construct test bench including scoreboard, agents, sequencers, and monitors for new blocks
• Write test plan, develop test cases, debug regression failures and drive to module verification closure
• Ensuring complete verification coverage through implementation and review of code and functional coverage

Skills

SystemVerilog

UVM

Perl

Python

Education

Bachelor's degree in ASIC Design/Verification

Job description

Cisco Systems, Inc is seeking an ASIC Engineer to play a critical role in developing Cisco’s data center solutions. You will collaborate with verification engineers, designers, hardware, and other cross-functional teams to verify the ASIC in simulation, emulation, and bring-up to ensure seamless integration and optimal performance of Cisco’s hardware platforms.

You will maintain DV environments, construct test benches, write test plans, debug regressions, and drive verification closure, while