Design Verification Engineer - Interface IP

The Consensus; Austin (TX); Hybrid; USD 130,000 - 170,000; Full time

Benefits offered by this job

Health benefits

$500 monthly waiver credit

Wellness programs

Daily meals in office

Compute budget

Job summary

Etched is seeking a Design Verification Engineer to join the Interface IP DV team in Austin, with hybrid collaboration across San Jose. You will verify IP subsystems, ensure correctness across the hardware-software stack, and tackle challenging verification tasks in a fast-paced startup setting.

You will own verification of multiple IP subsystems, develop scalable testbenches, and collaborate with RTL, software, and emulation teams to ensure robust integration and performance across the chip

Qualifications

• 5+ years of design verification experience.
• Strong ability to tackle complex verification challenges and expose corner-case bugs.
• Hands-on experience with SystemVerilog/UVM and building scalable, reusable testbenches.
• Familiarity with IP interfaces and protocols like PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs.

Responsibilities

• End-to-end ownership of IP subsystems (PCIe, Ethernet, CPU, low power peripherals, sensors).
• Understand vendor IP configurations and handshake with internal IP team.
• Develop and maintain UVM/SystemVerilog verification environments for functional correctness and performance.
• Collaborate with integration and SoC DV teams to validate IP interactions within the chip architecture.
• Drive coverage closure and sign-off by defining metrics and analyzing gaps across corner cases.

Skills

SystemVerilog

UVM

IP verification

PCIe

Ethernet

AXI/AMBA

ARM/ARC CPUs

Collaboration

Job description

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges.

Key responsibilities

• End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors

• Understand vendor IP configurations and handle handshake with internal IP team

• Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.

• Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture.

• Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios.

You may be a good fit if you have

• 5+ years of design verification experience

• You enjoy digging deep into complex verification challenges and finding creative ways to expose corner-case bugs.

• You have hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches.

• You are comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs.

• You thrive in a fast-paced startup environment and can take ownership of projects with minimal direction.

• You collaborate naturally with cross-functional teams — from RTL design to software and emulation — and can clearly communicate technical insights.
  

Strong candidates may also have experience with

• Experience handling vendors and integration of IP/VIP’s

• UVM/System Verilog

Benefits

• Medical, dental, and vision packages with generous premium coverage

  • $500 per month credit for waiving medical benefits

• Various wellness benefits covering fitness, mental health, and more

• Daily lunch + dinner in our office

• Unlimited compute budget subject to ROI justification

How we’re different

Etched believes in Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.

We greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.