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Piper Companies is seeking an IC Package Design Engineer onsite near San Jose, CA to lead the physical layout of advanced multi-die substrates and chiplet integration.
The ideal candidate will collaborate with ASIC, signal, power, and mechanical teams and must have 8+ years of substrate layout experience with U.S. work eligibility and an active Secret clearance ability. Proficiency in Siemens Xpedition and Cadence Allegro APD is required.
Piper Companies is seeking an IC Package Design Engineer onsite near San Jose, CA to lead the physical layout of advanced multi-die substrates and chiplet integration.
The ideal candidate will collaborate with ASIC, signal, power, and mechanical teams and must have 8+ years of substrate layout experience with U.S. work eligibility and an active Secret clearance ability. Proficiency in Siemens Xpedition and Cadence Allegro APD is required.