IC Design Verification Engineer

WinMax Systems Corporation; San Jose (CA); On-site; USD 100,000 - 130,000; Full time

Job summary

A leading technology firm in San Jose is looking for a skilled engineer to enhance verification methodologies for unit-level MAC layer simulation. This role involves architecting and implementing test infrastructure and requires expertise in UVM verification environments and knowledge of networking protocols. Candidates should possess a BSCS/BSEE or equivalent with significant experience. This position offers an opportunity to work collaboratively in a dynamic environment with competitive compensation.

Qualifications

• Typically requires a BSCS/BSEE degree and 8 years of related experience.
• An MSCS/MSEE degree and 6 years of related experience is also accepted.
• Experience with establishing and managing coverage metrics is desirable.

Responsibilities

• Establish verification methodology for MAC layer simulation.
• Architect and implement infrastructure for test-benches and APIs.
• Establish metrics and implement tests for functional correctness.

Skills

UVM based verification environments

Knowledge of wired or wireless networking protocols

SystemVerilog

OO programming

Perl

Python

Tcl

C

Education

BSCS/BSEE degree

MSCS/MSEE degree

Tools

Logic simulators from Cadence

Logic simulators from Synopsys

Logic simulators from Mentor

Job description

Your primary job responsibility is to establish/enhance the verification methodology for unit-level MAC layer simulation and extend the methodology to SoC level simulation environments. In this role you will be architecting and implementing the infrastructure including test-benches, APIs, golden reference models, 802.11 specific protocol layer generators and checkers. You will also be responsible for establishing metrics and implementing tests for functional correctness, coverage, and performance characterization.

Typically requires a BSCS/BSEE degree and 8 years of related experience, an MSCS/MSEE degree and 6 years of related experience

Experience building UVM based verification environments – unit-level and SoC - for 802.11, Ethernet or other networking designs

Knowledge of wired or wireless networking protocols is desirable

Expert knowledge of HVLs: SystemVerilog/OVM/UVM is required and OO programming experience is a plus

Knowledge of assertion based (SVA, PSL based) methodologies – formal and simulation - is necessary

Experience in establishing and managing coverage requirements and achieving coverage metrics is desirable

Working knowledge of scripting in Perl, Python, Tcl, and C

Experience with logic simulators and debug tools from Cadence, Synopsys, and Mentor

Ability to effectively collaborate with multiple teams, across geographies, in a dynamic, fast paced development environment

Capability to learn new skills or technologies as needed and be self-motivated

Additional Information

All your information will be kept confidential according to EEO guidelines.