Hybrid VLSI Verification Intern: SystemVerilog/UVM

hpe; Chippewa Falls (WI); Hybrid; USD 48,000 - 56,000; Part time

Job summary

Hewlett Packard Enterprise is seeking a VLSI Design Verification Intern in Wisconsin. The role is hybrid, with an average of two days per week in an HPE office, and focuses on Slingshot interconnect, SystemVerilog, and UVM verification for a future ASIC.

You will work with architects and verification engineers, develop testbenches, write constrained-random tests, and analyze coverage. Ideal candidates are pursuing a BS or MS in EE, CE, or CS, with digital design, computer architecture

Qualifications

• Pursuing a bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• Coursework in digital design and computer architecture.
• Experience with object-oriented programming.
• Clear written and verbal communication skills.
• Willingness to ask questions, explain reasoning, and participate in technical discussions.

Responsibilities

• Develop SystemVerilog and UVM testbench components, including models, monitors, scoreboards, and checkers
• Write constrained-random tests
• Develop and analyze functional coverage to identify verification gaps
• Debug regression failures and help identify, log, and resolve logic bugs
• Work directly with ASIC designers and architects
• Use scripting, automation, and AI-assisted tools to improve the verification process

Skills

Object-oriented programming

Strong analytical skills

Excellent written and verbal

Willingness to ask questions

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science

Tools

Verilog

SystemVerilog

UVM

Python

Job description

Hewlett Packard Enterprise is seeking a VLSI Design Verification Intern in Wisconsin. The role is hybrid, with an average of two days per week in an HPE office, and focuses on Slingshot interconnect, SystemVerilog, and UVM verification for a future ASIC.

You will work with architects and verification engineers, develop testbenches, write constrained-random tests, and analyze coverage. Ideal candidates are pursuing a BS or MS in EE, CE, or CS, with digital design, computer architecture