Hybrid VLSI Physical Design Engineer - Timing & Flow

Hewlett Packard Enterprise; Fort Collins (CO); Hybride; USD 115 000 - 218 000; Plein temps

Résumé du poste

Hewlett Packard Enterprise is seeking a VLSI Physical Design Engineer in a hybrid role requiring you to work about 2 days per week from an HPE office in the United States. The role focuses on designing, verifying, and implementing ASICs with emphasis on timing, power, and area optimization.

You will analyze timing, perform synthesis and formal verification, and collaborate with cross-functional teams to deliver robust back-end flows and ECOs.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or equivalent.
• 1–6 years of experience in VLSI design, verification, or implementation.

Responsabilités

• Perform static timing analysis for hierarchical designs at partition and full-chip levels.
• Create, validate, and maintain timing constraints and timing budgets.
• Drive timing closure for partition-level and full-chip designs including setup, hold, clock, I/O, and test timing.
• Analyze timing reports, identify critical paths, and implement fixes for performance and power targets.
• Perform synthesis, netlist quality checks, and formal verification.
• Support chip partitioning, floorplanning, and physical design implementation.
• Create and manage ECOs.
• Develop flow automation and improve methodologies for synthesis, timing analysis, formal verification, and signoff.
• Partner with cross-functional teams to promote physical-design-aware architecture.
• Review design activities for compliance with ASIC standards; collaborate with external partners.
• Provide technical guidance and mentoring to less-experienced engineers.

Connaissances

VLSI design fundamentals

digital logic

computer architecture

analytical skills

problem solving

team collaboration

independent work

strong communication

Formation

Bachelor's or Master's degree in Electrical Engineering/Computer Engineering

Outils

Synopsys Fusion Compiler

Design Compiler

PrimeTime

Formality

Cadence RTL Compiler

Genus

LEC

Description du poste

Hewlett Packard Enterprise is seeking a VLSI Physical Design Engineer in a hybrid role requiring you to work about 2 days per week from an HPE office in the United States. The role focuses on designing, verifying, and implementing ASICs with emphasis on timing, power, and area optimization.

You will analyze timing, perform synthesis and formal verification, and collaborate with cross-functional teams to deliver robust back-end flows and ECOs.