Hybrid RTL Verification Engineer: Pre-Silicon UVM & RTL

Intel; Hillsboro (OR); Hybrid; USD 106,000 - 200,000; Full time

Benefits offered by this job

Stock bonuses

Health insurance

Retirement plan

Vacation

Job summary

Intel in Hillsboro, Oregon is seeking an Experienced Verification Engineer to design and validate RTL and pre-silicon environments for next-generation silicon. You will build scalable UVM testbenches, drive verification strategies, and collaborate across architecture, physical design, and post-silicon teams to ensure robust silicon deliverables.

You will develop power verification methodologies, craft SystemVerilog assertions, and work on end-to-end validation across multiple projects in a

Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, or a STEM-related field with a minimum of 1+ years of relevant experience.
• Bachelor's degree in Electrical Engineering, Computer Engineering, or a STEM-related field with a minimum of 3+ years of relevant experience.
• Experience with Pre-silicon logic validation using SystemVerilog and UVM.
• Experience in Digital design using Verilog and/or SystemVerilog.
• Experience with pre-silicon validation closure across multiple projects.
• Hands-on experience with UVM testbench design, with a focus on reusability and scalability.
• Experience with end-to-end validation strategies for complex digital systems.
• Experience with SystemVerilog Assertions (SVA) for coverage closure.
• Experience with coverage-driven verification methodologies.
• Scripting proficiency in Python, Perl, or TCL for design and verification automation.

Responsibilities

• Design & Develop Verification Environments – Build and maintain scalable, reusable UVM-based testbenches and test cases for complex mixed-signal CMOS designs at the block, subsystem, and SoC levels.
• Define Verification Strategy – Own and drive comprehensive verification plans for complex digital systems, ensuring thorough coverage closure across multiple projects.
• RTL Development & Integration – Develop RTL designs and integrate logic components into SoC architectures, collaborating with IP providers to validate IPs at the system level.
• Power Methodology – Develop and implement power verification methodologies for complex mixed-signal IPs using industry-standard frameworks.
• Assertion-Based Verification – Create and apply SystemVerilog Assertions (SVA) to strengthen coverage closure and improve overall verification quality.
• Debug & Root Cause Analysis – Identify, debug, and resolve pre-silicon failures, implementing corrective measures and driving issues to closure.
• Cross-Team Collaboration – Partner with architecture, physical design, and post-silicon teams to continuously improve verification strategies for complex architectural features.
• Continuous Improvement – Incorporate post-silicon learnings and feedback into enhanced pre-silicon verification methodologies.
• Documentation & Reviews – Maintain detailed test plans and lead technical reviews with design and architecture teams.

Skills

UVM testbench design

SystemVerilog

Verilog

Digital design

SVA (SystemVerilog Assertions)

Coverage-driven verification

Python/Perl/TCL scripting

End-to-end validation

Education

Master's degree in Electrical Engineering / Computer Engineering / STEM field

Bachelor's degree in Electrical Engineering / Computer Engineering / STEM field

Tools

UVM

Verilog/SystemVerilog

Python

Perl

TCL

Job description

Intel in Hillsboro, Oregon is seeking an Experienced Verification Engineer to design and validate RTL and pre-silicon environments for next-generation silicon. You will build scalable UVM testbenches, drive verification strategies, and collaborate across architecture, physical design, and post-silicon teams to ensure robust silicon deliverables.

You will develop power verification methodologies, craft SystemVerilog assertions, and work on end-to-end validation across multiple projects in a