SoC Verification Engineer — Presilicon Debug (Hybrid)

Intel Corporation; Austin, Northern (TX, KY); Hybrid; USD 142,000 - 200,000; Full time

Benefits offered by this job

Stock bonuses

Health insurance

Retirement plan

Job summary

Intel Corporation in Austin, Texas is seeking a SoC Design Verification Engineer to design scalable verification plans, build test benches, and execute tests to uncover issues before silicon tape-out.

You will collaborate with architects, RTL teams, and postsilicon groups, apply OVM/UVM methodologies, and drive improvements in presilicon verification, emulation, and system simulation to ensure robust performance.

Qualifications

• Bachelor's, Master's, or PhD with hands-on verification experience in SoC design.
• Experience with OVM/UVM methodologies, debugging, and test planning.

Responsibilities

• Define and develop scalable verification plans for blocks, subsystems, and SoCs.
• Create test benches and verification environments aligned with microarchitecture specs.
• Execute verification plans using emulation and system simulation models to uncover bugs.
• Debug and root‑cause presilicon failures and implement corrective actions.
• Collaborate with architects, RTL, postsilicon, and physical design teams to improve verification.
• Document and maintain test plans; drive technical reviews.
• Incorporate security coverage in test plans, including regression and debugging tests.
• Maintain and improve verification infrastructure and methodologies.

Skills

OVM/UVM

Debugging

Test planning

Communication

Education

Bachelor's degree in Electrical Engineering/Computer Engineering/CS

Master's degree in Electrical Engineering/Computer Engineering/CS

PhD in Electrical Engineering/Computer Engineering/CS

Tools

Emulation models

System simulation tools

Job description

Intel Corporation in Austin, Texas is seeking a SoC Design Verification Engineer to design scalable verification plans, build test benches, and execute tests to uncover issues before silicon tape-out.

You will collaborate with architects, RTL teams, and postsilicon groups, apply OVM/UVM methodologies, and drive improvements in presilicon verification, emulation, and system simulation to ensure robust performance.