RTL Verification Engineer

WinMax Systems Corporation; Austin (TX); On-site; USD 80,000 - 100,000; Full time

Job summary

WinMax Systems Corporation in Austin, Texas is seeking a design verification engineer for GPU units. Responsibilities include performing pre-silicon validation, writing tests, and debugging failures with modern verification methodologies.

The ideal candidate possesses a BSEE or higher degree, with at least 2 years of experience in design verification. Proficiency in System Verilog is essential, along with skills in C++ and Python/Perl.

Qualifications

• At least 2 years of industry experience in a design verification role.
• Good verbal and written communication skills.

Responsibilities

• Learn the architecture and micro architecture by studying specifications.
• Review unit level test plans; modify if necessary.
• Write tests outlined by test plan and enhance testbench.
• Debug test failures and report RTL failures.
• Enhance test benches to achieve coverage goals.
• Support debug of unit in upper levels of design hierarchy.

Skills

Modern verification methodologies (UVM/VMM/OVM)

Debugging RTL

System Verilog

C++

Python/Perl

Education

BSEE or higher degree

Job description

Perform pre-silicon validation of GPU unit(s).

Qualifications

Responsibilities Include:

• Learn the architecture and micro architecture by studying specifications and direct interaction with architects and logic designers.
• Review unit level test plans; modify if necessary.
• Write the tests outlined by test plan. Enhance testbench if necessary, e.g. add coverage assertions.
• Debug test failures, fix test or testbench if necessary. Report RTL failures to RTL designers. Confirm bug is fixed.
• Enhance test benches and tests to achieve coverage goals.
• Support debug of unit in upper levels of design hierarchy.

Experience Requirements:

• Has used modern verification methodologies such as UVM/VMM/OVM. UVM is preferred.
• Experience verifying and debugging RTL, preferably in context of CPU, GPU, video, display or signal processing system.
• Understanding of micro-architecture and logic design fundamentals, e.g. finite state machines, arithmetic data path pipelines.
• Composed functional coverage assertions, preferably using System Verilog.

The qualified candidate will possess the following:

• BSEE or higher degree.
• At least 2 years of industry experience in a design verification role.
• Proficient in System Verilog. C++, Python/Perl skills are also desirable.
• Good verbal and written communication skills.

Additional Information

All your information will be kept confidential according to EEO guidelines.