Hybrid Memory IP RTL Design Engineer

Experis; Boxborough (MA); Hybrid; USD 110,000 - 150,000; Full time

Benefits offered by this job

Medical

Vision Plan

401(k)

Weekly Pay

Hybrid work model

Diversity & inclusion commitment

Job summary

Experis is seeking a Hardware Design Engineer 2 in Boxborough, MA to support the Memory PHY team. You will design RTL for LPDDR and DDR IPs, develop digital architecture from concept to physical implementation, and collaborate with architects, hardware, and firmware engineers to integrate new features.

The ideal candidate has a Bachelor's or Master's in Electrical or Computer Engineering and experience with Verilog, SystemVerilog, C, and C++, plus knowledge of clocking architectures, CDC, and

Qualifications

• Bachelor’s or Master’s degree in Electrical or Computer Engineering or related field.
• Proficiency in Verilog, SystemVerilog, C and C++.
• Strong knowledge of clocking architectures, synchronization and CDC.
• Experience with synthesis, timing closure and digital design verification tools.
• Familiarity with SERDES, DDR, Memory Controller or MAC design is preferred.

Responsibilities

• Design RTL for high-speed memory I/O PHY interfaces, including LPDDR and DDR IPs.
• Develop digital architecture from concept to physical implementation, ensuring optimal performance.
• Collaborate with architects, hardware, and firmware engineers to integrate new features.
• Perform timing synthesis, physical implementation, and verification of memory interface designs.
• Debug design failures, identify root causes, and work with teams to resolve issues efficiently.

Skills

Verilog

SystemVerilog

C

C++

Clocking architectures

CDC methodology

Synthesis

Timing closure

Digital design verification tools

SERDES/DDR/Memory Controller/MAC

Education

Bachelor’s or Master’s in Electrical Engineering / Computer Engineering

Job description

Experis is seeking a Hardware Design Engineer 2 in Boxborough, MA to support the Memory PHY team. You will design RTL for LPDDR and DDR IPs, develop digital architecture from concept to physical implementation, and collaborate with architects, hardware, and firmware engineers to integrate new features.

The ideal candidate has a Bachelor's or Master's in Electrical or Computer Engineering and experience with Verilog, SystemVerilog, C, and C++, plus knowledge of clocking architectures, CDC, and