Firmware Design Engineer

ManpowerGroup Global, Inc.; Boxborough (MA); Hybrid; USD 110,000 - 145,000; Full time

Benefits offered by this job

Hybrid work model

Medical plan

Dental plan

Vision plan

401(k) with match

Weekly pay

Job summary

ManpowerGroup Global, Inc. is seeking a Hardware Design Engineer 2 to support the Memory PHY team. You will design RTL for high-speed memory I/O interfaces like LPDDR and DDR, and collaborate across hardware and firmware teams to deliver robust IPs.

The role emphasizes digital/analog design understanding, timing closure, and verification, with a hybrid work model requiring 2–3 days onsite.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• Experience with Verilog and SystemVerilog programming languages.
• Strong knowledge of clocking architectures, synchronization, and CDC methodology.
• Experience with synthesis, timing closure, and digital design verification tools.
• Familiarity with SERDES, DDR, Memory Controller, or MAC design is preferred.

Responsibilities

• Design RTL for high-speed memory I/O PHY interfaces, including LPDDR and DDR IPs.
• Develop digital architecture from concept to physical implementation, ensuring optimal performance.
• Collaborate with architects, hardware, and firmware engineers to integrate new features.
• Perform timing synthesis, physical implementation, and verification of memory interface designs.
• Debug design failures, identify root causes, and work with teams to resolve issues efficiently.

Skills

Verilog

SystemVerilog

C

C++

Education

Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering

Tools

Synthesis tools

Timing closure tools

Digital design verification tools

SERDES

DDR

Job description

Our client, a leading innovator in the technology industry, is seeking a passionate and skilled Hardware Design Engineer 2 to join their dynamic team. As a Hardware Design Engineer 2, you will be supporting the Memory PHY team, contributing to the development of industry-leading high-speed memory interface IPs. This role offers an exciting opportunity to work on cutting-edge memory interface designs, collaborate with diverse engineering teams, and enhance your expertise in digital and analog design. The ideal candidate will demonstrate strong analytical skills, excellent communication, and a collaborative spirit, aligning well with our organization’s commitment to innovation and inclusivity.

Job Title: Hardware Design Engineer 2

Location: Boxborough, MA

Pay Range:

What's the Job?

• Design RTL for high-speed memory I/O PHY interfaces, including LPDDR and DDR IPs
• Develop digital architecture from concept to physical implementation, ensuring optimal performance
• Collaborate with architects, hardware, and firmware engineers to integrate new features
• Perform timing synthesis, physical implementation, and verification of memory interface designs
• Debug design failures, identify root causes, and work with teams to resolve issues efficiently

What's Needed?

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
• Experience with Verilog, SystemVerilog, C, and C++ programming languages
• Strong knowledge of clocking architectures, synchronization, and CDC methodology
• Experience with synthesis, timing closure, and digital design verification tools
• Familiarity with SERDES, DDR, Memory Controller, or MAC design is preferred

What's in it for me?

• Opportunity to work on industry-leading memory interface IPs and innovative projects
• Collaborative environment supporting professional growth and development
• Engagement with a talented team of engineers and industry experts
• Hybrid work model with 2-3 days onsite to foster teamwork and collaboration
• Participation in a company committed to diversity, inclusion, and ethical practices

Upon completion of waiting period, consultants are eligible for:

• Medical and Prescription Drug Plans
• Dental Plan
• Vision Plan
• 401(k), Plus Match
• Weekly Pay