Memory PHY RTL Design Engineer - Hybrid (LPDDR/DDR IPs)

TekWissen ®; Boxborough (MA); Hybrid; USD 69,000 - 83,000; Full time

Job summary

TekWissen Group is seeking a PHY Memory RTL Design Engineer for a 12-month hybrid assignment in Boxborough, MA. The role focuses on RTL and firmware development for high-speed LPDDR/DDR IPs, with responsibilities spanning design, verification, and physical implementation.

The candidate will collaborate with architects, hardware, and firmware teams across sites and time zones. The ideal candidate has strong Verilog/SystemVerilog skills, experience with timing closure and synthesis, and a solid

Qualifications

• Experience with RTL design and verification for high-speed memory IPs.
• Strong knowledge of Verilog/SystemVerilog, clocking architectures, and CDC methodologies.
• Experience with synthesis, timing closure, and debugging RTL/FW in collaboration with cross-functional teams.

Responsibilities

• RTL design for memory I/O.
• PHY Digital Architecture development from pathfinding to physical implementation.
• PHY link layer design, implementation & verification with Analog and System architect.
• PHY Analog/Digital co-design.
• Digital design and RTL coding.
• Timing Synthesis & Drive Physical implementation.
• Collaborate with architects, hardware and firmware engineers on new features to verify.
• Estimate time to write new feature tests and test environment changes.
• Build unit tests.
• Debug design failures with DV and firmware teams.

Skills

Verilog

SystemVerilog

C

C++

Python

Perl

TCL

Clocking architecture

CDC methodology

Synthesis

Timing closure

DDR/SerDes

Memory controller

RTL debugging

System architecture

Leadership

Education

Bachelors/Masters in Electrical/Computer Engineering

Job description

TekWissen Group is seeking a PHY Memory RTL Design Engineer for a 12-month hybrid assignment in Boxborough, MA. The role focuses on RTL and firmware development for high-speed LPDDR/DDR IPs, with responsibilities spanning design, verification, and physical implementation.

The candidate will collaborate with architects, hardware, and firmware teams across sites and time zones. The ideal candidate has strong Verilog/SystemVerilog skills, experience with timing closure and synthesis, and a solid