Memory IP Design Engineer - RTL & FW Expert

Trilyon, Inc.; Boxborough (MA); On-site; USD 120,000 - 180,000; Full time

Job summary

Trilyon, Inc. seeks a Design Engineer to lead RTL and firmware development for high-speed LPDDR/DDR memory IPs. You will participate in definition, design and validation, create IO designs, and work across multiple projects to improve methods.

The role requires strong Verilog/SystemVerilog, C/C++, and scripting skills, with experience in timing closure, synthesis, and memory interfaces. You will collaborate with architects, hardware and firmware engineers to deliver industry-leading IP.

Qualifications

• Proficient in Verilog and SystemVerilog
• Experience with C/C++ and scripting languages (Python/Perl/TCL)
• Knowledge of clocking architectures and CDC
• Experience with synthesis and timing closure
• SERDES/ DDR/Memory Controller or MAC design experience
• Strong debugging of firmware and RTL
• Solid understanding of computer organization/architecture
• Experience with mixed signal RTL and low power design
• Exposure to leadership or mentorship is a plus

Responsibilities

• RTL design for memory I/O
• PHY Digital Architecture development from pathfinding to physical implementation
• PHY link layer design, implementation & verification with Analog and System architect
• PHY Analog/Digital co-design
• Digital design and RTL coding
• Timing Synthesis & Drive Physical implementation
• Collaborate with architects, hardware and firmware engineers
• Estimate time to write new feature tests and test environment changes
• Build unit tests
• Debug design failures with DV and firmware engineers

Skills

Verilog

SystemVerilog

C

C++

Python

Perl

TCL

Clocking architectures

CDC methodology

Synthesis

Timing closure

SERDES

DDR

Memory Controller

MAC Design

Firmware debugging

RTL debugging

Computer Architecture

Mixed signal RTL

Low power design

Leadership

Job description

Trilyon, Inc. seeks a Design Engineer to lead RTL and firmware development for high-speed LPDDR/DDR memory IPs. You will participate in definition, design and validation, create IO designs, and work across multiple projects to improve methods.

The role requires strong Verilog/SystemVerilog, C/C++, and scripting skills, with experience in timing closure, synthesis, and memory interfaces. You will collaborate with architects, hardware and firmware engineers to deliver industry-leading IP.